package hardcaml_step_testbench

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hardcaml_step_testbench
- Library hardcaml_step_testbench
  - Hardcaml_step_testbench
    
    Before_and_after_edge
    
    Step_monads
    
    S
    
    Input_monad
    
    Step_monad
    
    Input_monad
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    Functional
    
    S
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    I
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    O
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    M
    
    S
    
    Step_monad
    
    I
    
    O
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Make
    
    Step_monad
    
    I
    
    O
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Cyclesim
    
    Monads
    
    Input_monad
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    M
    
    S
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    I
    
    O
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulator
    
    S
    
    Step_monad
    
    I
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    O
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulator
    
    Make
    
    Step_monad
    
    I
    
    O
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulator
    
    Event_driven_sim
    
    Monads
    
    Input_monad
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    M
    
    S
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    I
    
    O
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulation_step
    
    Logic
    
    Simulator
    
    Config
    
    Event_simulator
    
    Logic
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Ops
    
    Vcd
    
    With_interface
    
    Input
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Output
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Logic
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Ops
    
    S
    
    Step_monad
    
    I
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    O
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulation_step
    
    Make
    
    Step_monad
    
    I
    
    O
    
    I_data
    
    O_data
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulation_step
    
    Imperative
    
    S
    
    No_data
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    M
    
    S
    
    No_data
    
    Step_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Make
    
    No_data
    
    Step_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Cyclesim
    
    Monads
    
    Input_monad
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    S
    
    No_data
    
    Step_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    No_data
    
    Step_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Event_driven_sim
    
    Monads
    
    Input_monad
    
    Step_monad
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    Logic
    
    Simulator
    
    Config
    
    Event_simulator
    
    Logic
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Ops
    
    Vcd
    
    With_interface
    
    Input
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Output
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Logic
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Ops
    
    S
    
    No_data
    
    Step_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulation_step
    
    No_data
    
    Step_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Array
    
    Simulation_step
- Library hardcaml_step_testbench.digital_components
  - Digital_components
    
    Component
    
    Module
    
    S
    
    Input
    
    Output
    
    M
    
    S
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Make
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Data
    
    S
    
    Bool
    
    Int
    
    String
    
    Unit
    
    Pair
    
    Step_monad
    
    S
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    M
    
    S
    
    Input_monad
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
    
    Make
    
    Input_monad
    
    Component
    
    Input_monad
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Next_input
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Output
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Output
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Event
    
    Component_finished
- Sources
  - hardcaml_step_testbench
    
    before_and_after_edge.ml
    
    functional.ml
    
    functional_cyclesim.ml
    
    functional_cyclesim_intf.ml
    
    functional_event_driven_sim.ml
    
    functional_event_driven_sim_intf.ml
    
    functional_intf.ml
    
    hardcaml_step_testbench.ml
    
    hardcaml_step_testbench__.ml
    
    imperative.ml
    
    imperative_cyclesim.ml
    
    imperative_cyclesim_intf.ml
    
    imperative_event_driven_sim.ml
    
    imperative_event_driven_sim_intf.ml
    
    imperative_intf.ml
    
    step_monads.ml
  - hardcaml_step_testbench.digital_components
    
    component.ml
    
    component_intf.ml
    
    data.ml
    
    data_intf.ml
    
    digital_components.ml
    
    digital_components__.ml
    
    step_monad.ml
    
    step_monad_intf.ml

Legend:
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Module type
Parameter
Class
Class type
Source

Module `Hardcaml_step_testbench.Functional`Source

include module type of struct include Functional end

Sourcemodule type S = Functional.S

Source

module M
  (Monads : Step_monads.S)
  (I : Hardcaml.Interface.S)
  (O : Hardcaml.Interface.S) : 
  sig ... end

Source

module Make
  (Monads : Step_monads.S)
  (I : Hardcaml.Interface.S)
  (O : Hardcaml.Interface.S) : 
  sig ... end

Sourcemodule Cyclesim : sig ... end

Sourcemodule Event_driven_sim : sig ... end

package hardcaml_step_testbench

Module Hardcaml_step_testbench.FunctionalSource

Module `Hardcaml_step_testbench.Functional`Source