package hardcaml_xilinx_reports

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1. Library hardcaml_xilinx_reports

package hardcaml_xilinx_reports

hardcaml_xilinx_reports
- Library hardcaml_xilinx_reports
  - Hardcaml_xilinx_reports
    
    Clock
    
    Command
    
    Command_flags
    
    With_interface
    
    Primitive_group
    
    Subgroup
    
    Advanced
    
    Variants
    
    Arithmetic
    
    Variants
    
    Blockram
    
    Variants
    
    Clb
    
    Variants
    
    Clock
    
    Variants
    
    Configuration
    
    Variants
    
    Io
    
    Variants
    
    Register
    
    Variants
    
    Variants
    
    Project
    
    Config
    
    Report
    
    Subgroup
    
    Group
    
    Clock
    
    Wrap_with_registers
    
    Sequential_interface
    
    Data
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Make_sequential
    
    Make
    
    I_with_clock
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
- Sources
  - hardcaml_xilinx_reports
    
    clock.ml
    
    command.ml
    
    file_path_and_name.ml
    
    hardcaml_xilinx_reports.ml
    
    hardcaml_xilinx_reports__.ml
    
    import.ml
    
    primitive_group.ml
    
    project.ml
    
    report.ml
    
    wrap_with_registers.ml

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hardcaml_xilinx_reports

API

Library hardcaml_xilinx_reports

Hardcaml_xilinx_reports Run Vivado and create a synthesis timing and utilization report for a design.