package hardcaml_xilinx

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package hardcaml_xilinx
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Module Hardcaml_xilinx.SynthesisSource

Sourcemodule type Combinational_primitives = sig ... end
Sourcemodule type Sequential_primitives = sig ... end
Sourcemodule Lut_equation : sig ... end

Allow expressions to generate LUT init values

Hardcaml based models of Xilinx primitives

Unisim library based Xilinx primitives

Sourcemodule type Xilinx_primitives = sig ... end
Sourcemodule type Lut_size = sig ... end
Sourcemodule Make_sequential (Synth : Xilinx_primitives with type t = Hardcaml.Signal.t) : sig ... end
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