Height of BRAM cascades chains. This can be explicitly specified to help vivado meet timing when it is unnecessarily cascading BRAMs.

Single clock Dual Port Memory

A general-purpose means of representing memories. The Config.t type allows the user to configure the underlying memory implementations. Eg: Using URAM for bits 0-72, and BRAMs for bits 73-80. This module allows construction of memories in 1D or 2D Modes. See further documentation below.

Xilinx RAM primitive types.

Statemachine for clearing a RAM via one of it's ports.

Simple Dual Port Memory. 1 port is for writing, the other for reading.

True Dual Port Memory with independent clocks for ports a and b.