package hardcaml_verify

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package hardcaml_verify

hardcaml_verify
- Library hardcaml_verify
  - Hardcaml_verify
    
    Basic_gates
    
    Cnf
    
    Comb_gates
    
    Dimacs
    
    Is_one_hot
    
    Label
    
    Sat
    
    Sec
    
    Solver
    
    Tseitin
    
    Nusmv
    
    Proof_result
    
    Output_parser
    
    Circuit_properties
    
    With_interface
    
    Counter_example_trace
- Library hardcaml_verify.kernel
  - Hardcaml_verify_kernel
    
    Basic_gates
    
    Uid
    
    Cnf
    
    Literal
    
    Disjunction
    
    Conjunction
    
    Model
    
    Model_with_bits
    
    Model_with_vectors
    
    Comb_gates
    
    TypedMath
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Dimacs
    
    Is_one_hot
    
    Make
    
    Label
    
    Uid
    
    Nusmv
    
    Counter_example_trace
    
    Proof_result
    
    Output_parser
    
    Circuit_properties
    
    With_interface
    
    Sat
    
    Sec
    
    Instantiation_ports_match
    
    Proposition
    
    Equivalence_result
    
    Solver
    
    Tseitin
    
    S
    
    Make
- Sources
  - hardcaml_verify
    
    hardcaml_verify.ml
    
    hardcaml_verify__.ml
    
    nusmv.ml
  - hardcaml_verify.kernel
    
    basic_gates.ml
    
    cnf.ml
    
    comb_gates.ml
    
    config.ml
    
    dimacs.ml
    
    hardcaml_verify_kernel.ml
    
    hardcaml_verify_kernel__.ml
    
    is_one_hot.ml
    
    label.ml
    
    nusmv.ml
    
    sat.ml
    
    sec.ml
    
    solver.ml
    
    tseitin.ml
    
    uid.ml

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Module `Sec.Proposition`Source

A proposition derived from the circuits being compared.

Sourcetype t

Sourceval sexp_of_t : t -> Sexplib0.Sexp.t