package xedbindings
Bindings to Intel XED
Install
Dune Dependency
Authors
Maintainers
Sources
ocaml-xed-bindings-v0.9.tgz
sha256=180f7a952a55eeccd58190f808a066e3fdab93e94436037b4e88d5a9d0db09af
doc/src/xedbindings.bind/XBEnums.ml.html
Source file XBEnums.ml
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"address_width_of_int: no enum for given int" type attribute = | INVALID | AMDONLY | APX_NDD | APX_NF | ATOMIC | ATT_OPERAND_ORDER_EXCEPTION | BROADCAST_ENABLED | BYTEOP | DISP8_EIGHTHMEM | DISP8_FULL | DISP8_FULLMEM | DISP8_GPR_READER | DISP8_GPR_READER_BYTE | DISP8_GPR_READER_WORD | DISP8_GPR_WRITER_LDOP_D | DISP8_GPR_WRITER_LDOP_Q | DISP8_GPR_WRITER_STORE | DISP8_GPR_WRITER_STORE_BYTE | DISP8_GPR_WRITER_STORE_WORD | DISP8_GSCAT | DISP8_HALF | DISP8_HALFMEM | DISP8_MEM128 | DISP8_MOVDDUP | DISP8_NO_SCALE | DISP8_QUARTER | DISP8_QUARTERMEM | DISP8_SCALAR | DISP8_TUPLE1 | DISP8_TUPLE1_4X | DISP8_TUPLE1_BYTE | DISP8_TUPLE1_WORD | DISP8_TUPLE2 | DISP8_TUPLE4 | DISP8_TUPLE8 | DOUBLE_WIDE_MEMOP | DOUBLE_WIDE_OUTPUT | DWORD_INDICES | ELEMENT_SIZE_D | ELEMENT_SIZE_Q | EXCEPTION_BR | FAR_XFER | FIXED_BASE0 | FIXED_BASE1 | FIXED_ROUNDING_RNE | FLUSH_INPUT_DENORM | FLUSH_OUTPUT_DENORM | GATHER | HALF_WIDE_OUTPUT | HLE_ACQ_ABLE | HLE_REL_ABLE | IGNORES_OSFXSR | IMPLICIT_ONE | INDEX_REG_IS_POINTER | INDIRECT_BRANCH | KMASK | LOCKABLE | LOCKED | MASKOP | MASKOP_EVEX | MASK_AS_CONTROL | MASK_VARIABLE_MEMOP | MEMORY_FAULT_SUPPRESSION | MMX_EXCEPT | MPX_PREFIX_ABLE | MULTIDEST2 | MULTISOURCE4 | MXCSR | MXCSR_RD | NONTEMPORAL | NOP | NOTSX | NOTSX_COND | NO_REG_MATCH | NO_RIP_REL | NO_SRC_DEST_MATCH | PREFETCH | PROTECTED_MODE | QWORD_INDICES | REP | REQUIRES_ALIGNMENT | REQUIRES_ALIGNMENT_4B | REQUIRES_ALIGNMENT_8B | RING0 | SCALABLE | SCATTER | SIMD_SCALAR | SKIPLOW32 | SKIPLOW64 | SPECIAL_AGEN_REQUIRED | STACKPOP0 | STACKPOP1 | STACKPUSH0 | STACKPUSH1 | UNDOCUMENTED | USES_DAZ | USES_FTZ | X87_CONTROL | X87_MMX_STATE_CW | X87_MMX_STATE_R | X87_MMX_STATE_W | X87_NOWAIT | XMM_STATE_CW | XMM_STATE_R | XMM_STATE_W let attribute_len = 105 let attribute_to_int : attribute -> int = Obj.magic let attribute_of_int (x : int) : attribute = if 0 <= x && x < 105 then Obj.magic x else failwith "attribute_of_int: no enum for given int" type category = | INVALID | AMD3DNOW | ADOX_ADCX | AES | AMX_TILE | APX | AVX | AVX2 | AVX2GATHER | AVX512 | AVX512_4FMAPS | AVX512_4VNNIW | AVX512_BITALG | AVX512_VBMI | AVX512_VP2INTERSECT | AVX_IFMA | BINARY | BITBYTE | BLEND | BMI1 | BMI2 | BROADCAST | CALL | CET | CLDEMOTE | CLFLUSHOPT | CLWB | CLZERO | CMOV | COMPRESS | COND_BR | CONFLICT | CONVERT | DATAXFER | DECIMAL | ENQCMD | EXPAND | FCMOV | FLAGOP | FMA4 | FP16 | FRED | GATHER | GFNI | HRESET | IFMA | INTERRUPT | IO | IOSTRINGOP | KEYLOCKER | KEYLOCKER_WIDE | KMASK | LEGACY | LKGS | LOGICAL | LOGICAL_FP | LZCNT | MISC | MMX | MOVDIR | MPX | MSRLIST | NOP | PBNDKB | PCLMULQDQ | PCONFIG | PKU | POP | PREFETCH | PREFETCHWT1 | PTWRITE | PUSH | RDPID | RDPRU | RDRAND | RDSEED | RDWRFSGS | RET | ROTATE | SCATTER | SEGOP | SEMAPHORE | SERIALIZE | SETCC | SGX | SHA | SHA512 | SHIFT | SMAP | SSE | STRINGOP | STTNI | SYSCALL | SYSRET | SYSTEM | TBM | TSX_LDTRK | UINTR | UNCOND_BR | USER_MSR | VAES | VBMI2 | VEX | VFMA | VIA_PADLOCK | VPCLMULQDQ | VTX | WAITPKG | WIDENOP | WRMSRNS | X87_ALU | XOP | XSAVE | XSAVEOPT let category_len = 114 let category_to_int : category -> int = Obj.magic let category_of_int (x : int) : category = if 0 <= x && x < 114 then Obj.magic x else failwith "category_of_int: no enum for given int" type chip = | INVALID | I86 | I86FP | I186 | I186FP | I286REAL | I286 | I2186FP | I386REAL | I386 | I386FP | I486REAL | I486 | PENTIUMREAL | PENTIUM | QUARK | PENTIUMMMXREAL | PENTIUMMMX | ALLREAL | PENTIUMPRO | PENTIUM2 | PENTIUM3 | PENTIUM4 | P4PRESCOTT | P4PRESCOTT_NOLAHF | P4PRESCOTT_VTX | MEROM | PENRYN | PENRYN_E | NEHALEM | WESTMERE | BONNELL | SALTWELL | SILVERMONT | VIA | AMD_K10 | AMD_BULLDOZER | AMD_PILEDRIVER | AMD_ZEN | AMD_ZENPLUS | AMD_ZEN2 | AMD_FUTURE | GOLDMONT | GOLDMONT_PLUS | TREMONT | SNOW_RIDGE | LAKEFIELD | SANDYBRIDGE | IVYBRIDGE | HASWELL | BROADWELL | SKYLAKE | COMET_LAKE | SKYLAKE_SERVER | CASCADE_LAKE | COOPER_LAKE | KNL | KNM | CANNONLAKE | ICE_LAKE | ICE_LAKE_SERVER | TIGER_LAKE | ALDER_LAKE | SAPPHIRE_RAPIDS | EMERALD_RAPIDS | GRANITE_RAPIDS | SIERRA_FOREST | CLEARWATER_FOREST | ARROW_LAKE | LUNAR_LAKE | PANTHER_LAKE | FUTURE | ALL let chip_len = 73 let chip_to_int : chip -> int = Obj.magic let chip_of_int (x : int) : chip = if 0 <= x && x < 73 then Obj.magic x else failwith "chip_of_int: no enum for given int" type cpuid_group = | INVALID | ADOX_ADCX | AES | AMX_BF16 | AMX_COMPLEX | AMX_FP16 | AMX_INT8 | AMX_TILE | APX_F | APX_F_ADX | APX_F_AMX | APX_F_BMI1 | APX_F_BMI2 | APX_F_CET | APX_F_CMPCCXADD | APX_F_ENQCMD | APX_F_INVPCID | APX_F_KOPB | APX_F_KOPB_AVX10 | APX_F_KOPD | APX_F_KOPD_AVX10 | APX_F_KOPQ | APX_F_KOPQ_AVX10 | APX_F_KOPW | APX_F_KOPW_AVX10 | APX_F_LZCNT | APX_F_MOVBE | APX_F_MOVDIR64B | APX_F_MOVDIRI | APX_F_POPCNT | APX_F_RAO_INT | APX_F_USER_MSR | APX_F_VMX | AVX | AVX2 | AVX2GATHER | AVX512BW_128 | AVX512BW_128N | AVX512BW_128N_AVX10 | AVX512BW_128_AVX10 | AVX512BW_256 | AVX512BW_256_AVX10 | AVX512BW_512 | AVX512BW_512_AVX10 | AVX512BW_KOPD | AVX512BW_KOPD_AVX10 | AVX512BW_KOPQ | AVX512BW_KOPQ_AVX10 | AVX512CD_128 | AVX512CD_128_AVX10 | AVX512CD_256 | AVX512CD_256_AVX10 | AVX512CD_512 | AVX512CD_512_AVX10 | AVX512DQ_128 | AVX512DQ_128N | AVX512DQ_128N_AVX10 | AVX512DQ_128_AVX10 | AVX512DQ_256 | AVX512DQ_256_AVX10 | AVX512DQ_512 | AVX512DQ_512_AVX10 | AVX512DQ_KOPB | AVX512DQ_KOPB_AVX10 | AVX512DQ_KOPW | AVX512DQ_KOPW_AVX10 | AVX512DQ_SCALAR | AVX512DQ_SCALAR_AVX10 | AVX512ER_512 | AVX512ER_SCALAR | AVX512F_128 | AVX512F_128N | AVX512F_128N_AVX10 | AVX512F_128_AVX10 | AVX512F_256 | AVX512F_256_AVX10 | AVX512F_512 | AVX512F_512_AVX10 | AVX512F_KOPW | AVX512F_KOPW_AVX10 | AVX512F_SCALAR | AVX512F_SCALAR_AVX10 | AVX512PF_512 | AVX512_4FMAPS_512 | AVX512_4FMAPS_SCALAR | AVX512_4VNNIW_512 | AVX512_BF16_128 | AVX512_BF16_128_AVX10 | AVX512_BF16_256 | AVX512_BF16_256_AVX10 | AVX512_BF16_512 | AVX512_BF16_512_AVX10 | AVX512_BITALG_128 | AVX512_BITALG_128_AVX10 | AVX512_BITALG_256 | AVX512_BITALG_256_AVX10 | AVX512_BITALG_512 | AVX512_BITALG_512_AVX10 | AVX512_FP16_128 | AVX512_FP16_128N | AVX512_FP16_128N_AVX10 | AVX512_FP16_128_AVX10 | AVX512_FP16_256 | AVX512_FP16_256_AVX10 | AVX512_FP16_512 | AVX512_FP16_512_AVX10 | AVX512_FP16_SCALAR | AVX512_FP16_SCALAR_AVX10 | AVX512_GFNI_128 | AVX512_GFNI_128_AVX10 | AVX512_GFNI_256 | AVX512_GFNI_256_AVX10 | AVX512_GFNI_512 | AVX512_GFNI_512_AVX10 | AVX512_IFMA_128 | AVX512_IFMA_128_AVX10 | AVX512_IFMA_256 | AVX512_IFMA_256_AVX10 | AVX512_IFMA_512 | AVX512_IFMA_512_AVX10 | AVX512_VAES_128 | AVX512_VAES_128_AVX10 | AVX512_VAES_256 | AVX512_VAES_256_AVX10 | AVX512_VAES_512 | AVX512_VAES_512_AVX10 | AVX512_VBMI2_128 | AVX512_VBMI2_128_AVX10 | AVX512_VBMI2_256 | AVX512_VBMI2_256_AVX10 | AVX512_VBMI2_512 | AVX512_VBMI2_512_AVX10 | AVX512_VBMI_128 | AVX512_VBMI_128_AVX10 | AVX512_VBMI_256 | AVX512_VBMI_256_AVX10 | AVX512_VBMI_512 | AVX512_VBMI_512_AVX10 | AVX512_VNNI_128 | AVX512_VNNI_128_AVX10 | AVX512_VNNI_256 | AVX512_VNNI_256_AVX10 | AVX512_VNNI_512 | AVX512_VNNI_512_AVX10 | AVX512_VP2INTERSECT_128 | AVX512_VP2INTERSECT_256 | AVX512_VP2INTERSECT_512 | AVX512_VPCLMULQDQ_128 | AVX512_VPCLMULQDQ_128_AVX10 | AVX512_VPCLMULQDQ_256 | AVX512_VPCLMULQDQ_256_AVX10 | AVX512_VPCLMULQDQ_512 | AVX512_VPCLMULQDQ_512_AVX10 | AVX512_VPOPCNTDQ_128 | AVX512_VPOPCNTDQ_128_AVX10 | AVX512_VPOPCNTDQ_256 | AVX512_VPOPCNTDQ_256_AVX10 | AVX512_VPOPCNTDQ_512 | AVX512_VPOPCNTDQ_512_AVX10 | AVXAES | AVX_GFNI | AVX_IFMA | AVX_NE_CONVERT | AVX_VNNI | AVX_VNNI_INT16 | AVX_VNNI_INT8 | BMI1 | BMI2 | CET | CLDEMOTE | CLFLUSHOPT | CLFSH | CLWB | CMOV | CMPCCXADD | CMPXCHG16B | ENQCMD | F16C | FCMOV | FCOMI | FMA | FRED | FXSAVE | FXSAVE64 | GFNI | HRESET | ICACHE_PREFETCH | INVPCID | KEYLOCKER | KEYLOCKER_WIDE | LAHF | LKGS | LONGMODE | LZCNT | MCOMMIT | MONITOR | MONITORX | MOVBE | MOVDIR64B | MOVDIRI | MPX | MSRLIST | PBNDKB | PCLMULQDQ | PCONFIG | PENTIUMMMX | PKU | POPCNT | PREFETCHW | PREFETCHWT1 | PTWRITE | RAO_INT | RDPID | RDPRU | RDRAND | RDSEED | RDTSCP | RDWRFSGS | RTM | SEP | SERIALIZE | SGX | SHA | SHA512 | SM3 | SM4 | SMAP | SMX | SNP | SSE | SSE2 | SSE2MMX | SSE3 | SSE3X87 | SSE4 | SSE42 | SSE4A | SSEMXCSR | SSSE3 | SSSE3MMX | TSX_LDTRK | UINTR | USER_MSR | VAES | VIA_PADLOCK_AES | VIA_PADLOCK_MONTMUL | VIA_PADLOCK_RNG | VIA_PADLOCK_SHA | VPCLMULQDQ | VTX | WAITPKG | WBNOINVD | WRMSRNS | XSAVE | XSAVEC | XSAVEOPT | XSAVES let cpuid_group_len = 257 let cpuid_group_to_int : cpuid_group -> int = Obj.magic let cpuid_group_of_int (x : int) : cpuid_group = if 0 <= x && x < 257 then Obj.magic x else failwith "cpuid_group_of_int: no enum for given int" type cpuid_rec = | INVALID | ADOXADCX | AES | AMX_BF16 | AMX_COMPLEX | AMX_FP16 | AMX_INT8 | AMX_TILES | APX_F | AVX | AVX10_128VL | AVX10_256VL | AVX10_512VL | AVX10_ENABLED | AVX10_VER1 | AVX2 | AVX512BW | AVX512CD | AVX512DQ | AVX512ER | AVX512F | AVX512IFMA | AVX512PF | AVX512VBMI | AVX512VL | AVX512_4FMAPS | AVX512_4VNNIW | AVX512_BITALG | AVX512_FP16 | AVX512_VBMI2 | AVX512_VNNI | AVX512_VP2INTERSECT | AVX512_VPOPCNTDQ | AVX_IFMA | AVX_NE_CONVERT | AVX_VNNI | AVX_VNNI_INT16 | AVX_VNNI_INT8 | BF16 | BMI1 | BMI2 | CET | CLDEMOTE | CLFLUSH | CLFLUSHOPT | CLWB | CMOV | CMPCCXADD | CMPXCHG16B | ENQCMD | F16C | FMA | FPU | FRED | FXSAVE | GFNI | HRESET | ICACHE_PREFETCH | INTEL64 | INTELPT | INVPCID | KLENABLED | KLSUPPORTED | KLWIDE | LAHF | LKGS | LZCNT | MCOMMIT | MMX | MONITOR | MONITORX | MOVDIR64B | MOVDIRI | MOVEBE | MPX | MSRLIST | OSPKU | OSXSAVE | PBNDKB | PCLMULQDQ | PCONFIG | PKU | POPCNT | PREFETCHW | PREFETCHWT1 | PTWRITE | RAO_INT | RDP | RDPRU | RDRAND | RDSEED | RDTSCP | RDWRFSGS | RTM | SEP | SERIALIZE | SGX | SHA | SHA512 | SM3 | SM4 | SMAP | SMX | SNP | SSE | SSE2 | SSE3 | SSE4 | SSE42 | SSE4A | SSSE3 | TSX_LDTRK | UINTR | USER_MSR | VAES | VIA_PADLOCK_AES | VIA_PADLOCK_AES_EN | VIA_PADLOCK_PMM | VIA_PADLOCK_PMM_EN | VIA_PADLOCK_RNG | VIA_PADLOCK_RNG_EN | VIA_PADLOCK_SHA | VIA_PADLOCK_SHA_EN | VMX | VPCLMULQDQ | WAITPKG | WBNOINVD | WRMSRNS | XSAVE | XSAVEC | XSAVEOPT | XSAVES let cpuid_rec_len = 132 let cpuid_rec_to_int : cpuid_rec -> int = Obj.magic let cpuid_rec_of_int (x : int) : cpuid_rec = if 0 <= x && x < 132 then Obj.magic x else failwith "cpuid_rec_of_int: no enum for given int" type error = | NONE | BUFFER_TOO_SHORT | GENERAL_ERROR | INVALID_FOR_CHIP | BAD_REGISTER | BAD_LOCK_PREFIX | BAD_REP_PREFIX | BAD_LEGACY_PREFIX | BAD_REX_PREFIX | BAD_MAP | BAD_EVEX_V_PRIME | BAD_EVEX_Z_NO_MASKING | NO_OUTPUT_POINTER | NO_AGEN_CALL_BACK_REGISTERED | BAD_MEMOP_INDEX | CALLBACK_PROBLEM | GATHER_REGS | INSTR_TOO_LONG | INVALID_MODE | BAD_EVEX_LL | BAD_REG_MATCH let error_len = 21 let error_to_int : error -> int = Obj.magic let error_of_int (x : int) : error = if 0 <= x && x < 21 then Obj.magic x else failwith "error_of_int: no enum for given int" type extension = | INVALID | AMD3DNOW | A3DNOW_PREFETCH | ADOX_ADCX | AES | AMD_INVLPGB | AMX_TILE | APXEVEX | APXLEGACY | AVX | AVX2 | AVX2GATHER | AVX512EVEX | AVX512VEX | AVXAES | AVX_IFMA | AVX_NE_CONVERT | AVX_VNNI | AVX_VNNI_INT16 | AVX_VNNI_INT8 | BASE | BMI1 | BMI2 | CET | CLDEMOTE | CLFLUSHOPT | CLFSH | CLWB | CLZERO | CMPCCXADD | ENQCMD | F16C | FMA | FMA4 | FRED | GFNI | HRESET | ICACHE_PREFETCH | INVPCID | KEYLOCKER | KEYLOCKER_WIDE | LKGS | LONGMODE | LZCNT | MCOMMIT | MMX | MONITOR | MONITORX | MOVBE | MOVDIR | MPX | MSRLIST | PAUSE | PBNDKB | PCLMULQDQ | PCONFIG | PKU | PREFETCHWT1 | PTWRITE | RAO_INT | RDPID | RDPRU | RDRAND | RDSEED | RDTSCP | RDWRFSGS | RTM | SERIALIZE | SGX | SGX_ENCLV | SHA | SHA512 | SM3 | SM4 | SMAP | SMX | SNP | SSE | SSE2 | SSE3 | SSE4 | SSE4A | SSSE3 | SVM | TBM | TDX | TSX_LDTRK | UINTR | USER_MSR | VAES | VIA_PADLOCK_AES | VIA_PADLOCK_MONTMUL | VIA_PADLOCK_RNG | VIA_PADLOCK_SHA | VMFUNC | VPCLMULQDQ | VTX | WAITPKG | WBNOINVD | WRMSRNS | X87 | XOP | XSAVE | XSAVEC | XSAVEOPT | XSAVES let extension_len = 106 let extension_to_int : extension -> int = Obj.magic let extension_of_int (x : int) : extension = if 0 <= x && x < 106 then Obj.magic x else failwith "extension_of_int: no enum for given int" type flag = | INVALID | Of | Sf | Zf | Af | Pf | Cf | Df | Vif | Iopl | If | Ac | Vm | Rf | Nt | Tf | Id | Vip | Fc0 | Fc1 | Fc2 | Fc3 let flag_len = 22 let flag_to_int : flag -> int = Obj.magic let flag_of_int (x : int) : flag = if 0 <= x && x < 22 then Obj.magic x else failwith "flag_of_int: no enum for given int" type flag_action = | INVALID | U | Tst | Mod | A0 | Pop | Ah | A1 let flag_action_len = 8 let flag_action_to_int : flag_action -> int = Obj.magic let flag_action_of_int (x : int) : flag_action = if 0 <= x && x < 8 then Obj.magic x else failwith "flag_action_of_int: no enum for given int" type iclass = | INVALID | AAA | AAD | AADD | AAM | AAND | AAS | ADC | ADCX | ADC_LOCK | ADD | ADDPD | ADDPS | ADDSD | ADDSS | ADDSUBPD | ADDSUBPS | ADD_LOCK | ADOX | AESDEC | AESDEC128KL | AESDEC256KL | AESDECLAST | AESDECWIDE128KL | AESDECWIDE256KL | AESENC | AESENC128KL | AESENC256KL | AESENCLAST | AESENCWIDE128KL | AESENCWIDE256KL | AESIMC | AESKEYGENASSIST | AND | ANDN | ANDNPD | ANDNPS | ANDPD | ANDPS | AND_LOCK | AOR | ARPL | AXOR | BEXTR | BEXTR_XOP | BLCFILL | BLCI | BLCIC | BLCMSK | BLCS | BLENDPD | BLENDPS | BLENDVPD | BLENDVPS | BLSFILL | BLSI | BLSIC | BLSMSK | BLSR | BNDCL | BNDCN | BNDCU | BNDLDX | BNDMK | BNDMOV | BNDSTX | BOUND | BSF | BSR | BSWAP | BT | BTC | BTC_LOCK | BTR | BTR_LOCK | BTS | BTS_LOCK | BZHI | CALL_FAR | CALL_NEAR | CBW | CCMPB | CCMPBE | CCMPF | CCMPL | CCMPLE | CCMPNB | CCMPNBE | CCMPNL | CCMPNLE | CCMPNO | CCMPNS | CCMPNZ | CCMPO | CCMPS | CCMPT | CCMPZ | CDQ | CDQE | CFCMOVB | CFCMOVBE | CFCMOVL | CFCMOVLE | CFCMOVNB | CFCMOVNBE | CFCMOVNL | CFCMOVNLE | CFCMOVNO | CFCMOVNP | CFCMOVNS | CFCMOVNZ | CFCMOVO | CFCMOVP | CFCMOVS | CFCMOVZ | CLAC | CLC | CLD | CLDEMOTE | CLFLUSH | CLFLUSHOPT | CLGI | CLI | CLRSSBSY | CLTS | CLUI | CLWB | CLZERO | CMC | CMOVB | CMOVBE | CMOVL | CMOVLE | CMOVNB | CMOVNBE | CMOVNL | CMOVNLE | CMOVNO | CMOVNP | CMOVNS | CMOVNZ | CMOVO | CMOVP | CMOVS | CMOVZ | CMP | CMPBEXADD | CMPBXADD | CMPLEXADD | CMPLXADD | CMPNBEXADD | CMPNBXADD | CMPNLEXADD | CMPNLXADD | CMPNOXADD | CMPNPXADD | CMPNSXADD | CMPNZXADD | CMPOXADD | CMPPD | CMPPS | CMPPXADD | CMPSB | CMPSD | CMPSD_XMM | CMPSQ | CMPSS | CMPSW | CMPSXADD | CMPXCHG | CMPXCHG16B | CMPXCHG16B_LOCK | CMPXCHG8B | CMPXCHG8B_LOCK | CMPXCHG_LOCK | CMPZXADD | COMISD | COMISS | CPUID | CQO | CRC32 | CTESTB | CTESTBE | CTESTF | CTESTL | CTESTLE | CTESTNB | CTESTNBE | CTESTNL | CTESTNLE | CTESTNO | CTESTNS | CTESTNZ | CTESTO | CTESTS | CTESTT | CTESTZ | CVTDQ2PD | CVTDQ2PS | CVTPD2DQ | CVTPD2PI | CVTPD2PS | CVTPI2PD | CVTPI2PS | CVTPS2DQ | CVTPS2PD | CVTPS2PI | CVTSD2SI | CVTSD2SS | CVTSI2SD | CVTSI2SS | CVTSS2SD | CVTSS2SI | CVTTPD2DQ | CVTTPD2PI | CVTTPS2DQ | CVTTPS2PI | CVTTSD2SI | CVTTSS2SI | CWD | CWDE | DAA | DAS | DEC | DEC_LOCK | DIV | DIVPD | DIVPS | DIVSD | DIVSS | DPPD | DPPS | EMMS | ENCLS | ENCLU | ENCLV | ENCODEKEY128 | ENCODEKEY256 | ENDBR32 | ENDBR64 | ENQCMD | ENQCMDS | ENTER | ERETS | ERETU | EXTRACTPS | EXTRQ | F2XM1 | FABS | FADD | FADDP | FBLD | FBSTP | FCHS | FCMOVB | FCMOVBE | FCMOVE | FCMOVNB | FCMOVNBE | FCMOVNE | FCMOVNU | FCMOVU | FCOM | FCOMI | FCOMIP | FCOMP | FCOMPP | FCOS | FDECSTP | FDISI8087_NOP | FDIV | FDIVP | FDIVR | FDIVRP | FEMMS | FENI8087_NOP | FFREE | FFREEP | FIADD | FICOM | FICOMP | FIDIV | FIDIVR | FILD | FIMUL | FINCSTP | FIST | FISTP | FISTTP | FISUB | FISUBR | FLD | FLD1 | FLDCW | FLDENV | FLDL2E | FLDL2T | FLDLG2 | FLDLN2 | FLDPI | FLDZ | FMUL | FMULP | FNCLEX | FNINIT | FNOP | FNSAVE | FNSTCW | FNSTENV | FNSTSW | FPATAN | FPREM | FPREM1 | FPTAN | FRNDINT | FRSTOR | FSCALE | FSETPM287_NOP | FSIN | FSINCOS | FSQRT | FST | FSTP | FSTPNCE | FSUB | FSUBP | FSUBR | FSUBRP | FTST | FUCOM | FUCOMI | FUCOMIP | FUCOMP | FUCOMPP | FWAIT | FXAM | FXCH | FXRSTOR | FXRSTOR64 | FXSAVE | FXSAVE64 | FXTRACT | FYL2X | FYL2XP1 | GETSEC | GF2P8AFFINEINVQB | GF2P8AFFINEQB | GF2P8MULB | HADDPD | HADDPS | HLT | HRESET | HSUBPD | HSUBPS | IDIV | IMUL | IN | INC | INCSSPD | INCSSPQ | INC_LOCK | INSB | INSD | INSERTPS | INSERTQ | INSW | INT | INT1 | INT3 | INTO | INVD | INVEPT | INVLPG | INVLPGA | INVLPGB | INVPCID | INVVPID | IRET | IRETD | IRETQ | JB | JBE | JCXZ | JECXZ | JL | JLE | JMP | JMPABS | JMP_FAR | JNB | JNBE | JNL | JNLE | JNO | JNP | JNS | JNZ | JO | JP | JRCXZ | JS | JZ | KADDB | KADDD | KADDQ | KADDW | KANDB | KANDD | KANDNB | KANDND | KANDNQ | KANDNW | KANDQ | KANDW | KMOVB | KMOVD | KMOVQ | KMOVW | KNOTB | KNOTD | KNOTQ | KNOTW | KORB | KORD | KORQ | KORTESTB | KORTESTD | KORTESTQ | KORTESTW | KORW | KSHIFTLB | KSHIFTLD | KSHIFTLQ | KSHIFTLW | KSHIFTRB | KSHIFTRD | KSHIFTRQ | KSHIFTRW | KTESTB | KTESTD | KTESTQ | KTESTW | KUNPCKBW | KUNPCKDQ | KUNPCKWD | KXNORB | KXNORD | KXNORQ | KXNORW | KXORB | KXORD | KXORQ | KXORW | LAHF | LAR | LDDQU | LDMXCSR | LDS | LDTILECFG | LEA | LEAVE | LES | LFENCE | LFS | LGDT | LGS | LIDT | LKGS | LLDT | LLWPCB | LMSW | LOADIWKEY | LODSB | LODSD | LODSQ | LODSW | LOOP | LOOPE | LOOPNE | LSL | LSS | LTR | LWPINS | LWPVAL | LZCNT | MASKMOVDQU | MASKMOVQ | MAXPD | MAXPS | MAXSD | MAXSS | MCOMMIT | MFENCE | MINPD | MINPS | MINSD | MINSS | MONITOR | MONITORX | MOV | MOVAPD | MOVAPS | MOVBE | MOVD | MOVDDUP | MOVDIR64B | MOVDIRI | MOVDQ2Q | MOVDQA | MOVDQU | MOVHLPS | MOVHPD | MOVHPS | MOVLHPS | MOVLPD | MOVLPS | MOVMSKPD | MOVMSKPS | MOVNTDQ | MOVNTDQA | MOVNTI | MOVNTPD | MOVNTPS | MOVNTQ | MOVNTSD | MOVNTSS | MOVQ | MOVQ2DQ | MOVSB | MOVSD | MOVSD_XMM | MOVSHDUP | MOVSLDUP | MOVSQ | MOVSS | MOVSW | MOVSX | MOVSXD | MOVUPD | MOVUPS | MOVZX | MOV_CR | MOV_DR | MPSADBW | MUL | MULPD | MULPS | MULSD | MULSS | MULX | MWAIT | MWAITX | NEG | NEG_LOCK | NOP | NOP2 | NOP3 | NOP4 | NOP5 | NOP6 | NOP7 | NOP8 | NOP9 | NOT | NOT_LOCK | OR | ORPD | ORPS | OR_LOCK | OUT | OUTSB | OUTSD | OUTSW | PABSB | PABSD | PABSW | PACKSSDW | PACKSSWB | PACKUSDW | PACKUSWB | PADDB | PADDD | PADDQ | PADDSB | PADDSW | PADDUSB | PADDUSW | PADDW | PALIGNR | PAND | PANDN | PAUSE | PAVGB | PAVGUSB | PAVGW | PBLENDVB | PBLENDW | PBNDKB | PCLMULQDQ | PCMPEQB | PCMPEQD | PCMPEQQ | PCMPEQW | PCMPESTRI | PCMPESTRI64 | PCMPESTRM | PCMPESTRM64 | PCMPGTB | PCMPGTD | PCMPGTQ | PCMPGTW | PCMPISTRI | PCMPISTRI64 | PCMPISTRM | PCONFIG | PDEP | PEXT | PEXTRB | PEXTRD | PEXTRQ | PEXTRW | PEXTRW_SSE4 | PF2ID | PF2IW | PFACC | PFADD | PFCMPEQ | PFCMPGE | PFCMPGT | PFMAX | PFMIN | PFMUL | PFNACC | PFPNACC | PFRCP | PFRCPIT1 | PFRCPIT2 | PFRSQIT1 | PFRSQRT | PFSUB | PFSUBR | PHADDD | PHADDSW | PHADDW | PHMINPOSUW | PHSUBD | PHSUBSW | PHSUBW | PI2FD | PI2FW | PINSRB | PINSRD | PINSRQ | PINSRW | PMADDUBSW | PMADDWD | PMAXSB | PMAXSD | PMAXSW | PMAXUB | PMAXUD | PMAXUW | PMINSB | PMINSD | PMINSW | PMINUB | PMINUD | PMINUW | PMOVMSKB | PMOVSXBD | PMOVSXBQ | PMOVSXBW | PMOVSXDQ | PMOVSXWD | PMOVSXWQ | PMOVZXBD | PMOVZXBQ | PMOVZXBW | PMOVZXDQ | PMOVZXWD | PMOVZXWQ | PMULDQ | PMULHRSW | PMULHRW | PMULHUW | PMULHW | PMULLD | PMULLW | PMULUDQ | POP | POP2 | POP2P | POPA | POPAD | POPCNT | POPF | POPFD | POPFQ | POPP | POR | PREFETCHIT0 | PREFETCHIT1 | PREFETCHNTA | PREFETCHT0 | PREFETCHT1 | PREFETCHT2 | PREFETCHW | PREFETCHWT1 | PREFETCH_EXCLUSIVE | PREFETCH_RESERVED | PSADBW | PSHUFB | PSHUFD | PSHUFHW | PSHUFLW | PSHUFW | PSIGNB | PSIGND | PSIGNW | PSLLD | PSLLDQ | PSLLQ | PSLLW | PSMASH | PSRAD | PSRAW | PSRLD | PSRLDQ | PSRLQ | PSRLW | PSUBB | PSUBD | PSUBQ | PSUBSB | PSUBSW | PSUBUSB | PSUBUSW | PSUBW | PSWAPD | PTEST | PTWRITE | PUNPCKHBW | PUNPCKHDQ | PUNPCKHQDQ | PUNPCKHWD | PUNPCKLBW | PUNPCKLDQ | PUNPCKLQDQ | PUNPCKLWD | PUSH | PUSH2 | PUSH2P | PUSHA | PUSHAD | PUSHF | PUSHFD | PUSHFQ | PUSHP | PVALIDATE | PXOR | RCL | RCPPS | RCPSS | RCR | RDFSBASE | RDGSBASE | RDMSR | RDMSRLIST | RDPID | RDPKRU | RDPMC | RDPRU | RDRAND | RDSEED | RDSSPD | RDSSPQ | RDTSC | RDTSCP | REPE_CMPSB | REPE_CMPSD | REPE_CMPSQ | REPE_CMPSW | REPE_SCASB | REPE_SCASD | REPE_SCASQ | REPE_SCASW | REPNE_CMPSB | REPNE_CMPSD | REPNE_CMPSQ | REPNE_CMPSW | REPNE_SCASB | REPNE_SCASD | REPNE_SCASQ | REPNE_SCASW | REP_INSB | REP_INSD | REP_INSW | REP_LODSB | REP_LODSD | REP_LODSQ | REP_LODSW | REP_MONTMUL | REP_MOVSB | REP_MOVSD | REP_MOVSQ | REP_MOVSW | REP_OUTSB | REP_OUTSD | REP_OUTSW | REP_STOSB | REP_STOSD | REP_STOSQ | REP_STOSW | REP_XCRYPTCBC | REP_XCRYPTCFB | REP_XCRYPTCTR | REP_XCRYPTECB | REP_XCRYPTOFB | REP_XSHA1 | REP_XSHA256 | REP_XSTORE | RET_FAR | RET_NEAR | RMPADJUST | RMPUPDATE | ROL | ROR | RORX | ROUNDPD | ROUNDPS | ROUNDSD | ROUNDSS | RSM | RSQRTPS | RSQRTSS | RSTORSSP | SAHF | SALC | SAR | SARX | SAVEPREVSSP | SBB | SBB_LOCK | SCASB | SCASD | SCASQ | SCASW | SEAMCALL | SEAMOPS | SEAMRET | SENDUIPI | SERIALIZE | SETB | SETBE | SETL | SETLE | SETNB | SETNBE | SETNL | SETNLE | SETNO | SETNP | SETNS | SETNZ | SETO | SETP | SETS | SETSSBSY | SETZ | SFENCE | SGDT | SHA1MSG1 | SHA1MSG2 | SHA1NEXTE | SHA1RNDS4 | SHA256MSG1 | SHA256MSG2 | SHA256RNDS2 | SHL | SHLD | SHLX | SHR | SHRD | SHRX | SHUFPD | SHUFPS | SIDT | SKINIT | SLDT | SLWPCB | SMSW | SQRTPD | SQRTPS | SQRTSD | SQRTSS | STAC | STC | STD | STGI | STI | STMXCSR | STOSB | STOSD | STOSQ | STOSW | STR | STTILECFG | STUI | SUB | SUBPD | SUBPS | SUBSD | SUBSS | SUB_LOCK | SWAPGS | SYSCALL | SYSCALL_32 | SYSENTER | SYSEXIT | SYSRET | SYSRET64 | SYSRET_AMD | T1MSKC | TCMMIMFP16PS | TCMMRLFP16PS | TDCALL | TDPBF16PS | TDPBSSD | TDPBSUD | TDPBUSD | TDPBUUD | TDPFP16PS | TEST | TESTUI | TILELOADD | TILELOADDT1 | TILERELEASE | TILESTORED | TILEZERO | TLBSYNC | TPAUSE | TZCNT | TZMSK | UCOMISD | UCOMISS | UD0 | UD1 | UD2 | UIRET | UMONITOR | UMWAIT | UNPCKHPD | UNPCKHPS | UNPCKLPD | UNPCKLPS | URDMSR | UWRMSR | V4FMADDPS | V4FMADDSS | V4FNMADDPS | V4FNMADDSS | VADDPD | VADDPH | VADDPS | VADDSD | VADDSH | VADDSS | VADDSUBPD | VADDSUBPS | VAESDEC | VAESDECLAST | VAESENC | VAESENCLAST | VAESIMC | VAESKEYGENASSIST | VALIGND | VALIGNQ | VANDNPD | VANDNPS | VANDPD | VANDPS | VBCSTNEBF162PS | VBCSTNESH2PS | VBLENDMPD | VBLENDMPS | VBLENDPD | VBLENDPS | VBLENDVPD | VBLENDVPS | VBROADCASTF128 | VBROADCASTF32X2 | VBROADCASTF32X4 | VBROADCASTF32X8 | VBROADCASTF64X2 | VBROADCASTF64X4 | VBROADCASTI128 | VBROADCASTI32X2 | VBROADCASTI32X4 | VBROADCASTI32X8 | VBROADCASTI64X2 | VBROADCASTI64X4 | VBROADCASTSD | VBROADCASTSS | VCMPPD | VCMPPH | VCMPPS | VCMPSD | VCMPSH | VCMPSS | VCOMISD | VCOMISH | VCOMISS | VCOMPRESSPD | VCOMPRESSPS | VCVTDQ2PD | VCVTDQ2PH | VCVTDQ2PS | VCVTNE2PS2BF16 | VCVTNEEBF162PS | VCVTNEEPH2PS | VCVTNEOBF162PS | VCVTNEOPH2PS | VCVTNEPS2BF16 | VCVTPD2DQ | VCVTPD2PH | VCVTPD2PS | VCVTPD2QQ | VCVTPD2UDQ | VCVTPD2UQQ | VCVTPH2DQ | VCVTPH2PD | VCVTPH2PS | VCVTPH2PSX | VCVTPH2QQ | VCVTPH2UDQ | VCVTPH2UQQ | VCVTPH2UW | VCVTPH2W | VCVTPS2DQ | VCVTPS2PD | VCVTPS2PH | VCVTPS2PHX | VCVTPS2QQ | VCVTPS2UDQ | VCVTPS2UQQ | VCVTQQ2PD | VCVTQQ2PH | VCVTQQ2PS | VCVTSD2SH | VCVTSD2SI | VCVTSD2SS | VCVTSD2USI | VCVTSH2SD | VCVTSH2SI | VCVTSH2SS | VCVTSH2USI | VCVTSI2SD | VCVTSI2SH | VCVTSI2SS | VCVTSS2SD | VCVTSS2SH | VCVTSS2SI | VCVTSS2USI | VCVTTPD2DQ | VCVTTPD2QQ | VCVTTPD2UDQ | VCVTTPD2UQQ | VCVTTPH2DQ | VCVTTPH2QQ | VCVTTPH2UDQ | VCVTTPH2UQQ | VCVTTPH2UW | VCVTTPH2W | VCVTTPS2DQ | VCVTTPS2QQ | VCVTTPS2UDQ | VCVTTPS2UQQ | VCVTTSD2SI | VCVTTSD2USI | VCVTTSH2SI | VCVTTSH2USI | VCVTTSS2SI | VCVTTSS2USI | VCVTUDQ2PD | VCVTUDQ2PH | VCVTUDQ2PS | VCVTUQQ2PD | VCVTUQQ2PH | VCVTUQQ2PS | VCVTUSI2SD | VCVTUSI2SH | VCVTUSI2SS | VCVTUW2PH | VCVTW2PH | VDBPSADBW | VDIVPD | VDIVPH | VDIVPS | VDIVSD | VDIVSH | VDIVSS | VDPBF16PS | VDPPD | VDPPS | VERR | VERW | VEXP2PD | VEXP2PS | VEXPANDPD | VEXPANDPS | VEXTRACTF128 | VEXTRACTF32X4 | VEXTRACTF32X8 | VEXTRACTF64X2 | VEXTRACTF64X4 | VEXTRACTI128 | VEXTRACTI32X4 | VEXTRACTI32X8 | VEXTRACTI64X2 | VEXTRACTI64X4 | VEXTRACTPS | VFCMADDCPH | VFCMADDCSH | VFCMULCPH | VFCMULCSH | VFIXUPIMMPD | VFIXUPIMMPS | VFIXUPIMMSD | VFIXUPIMMSS | VFMADD132PD | VFMADD132PH | VFMADD132PS | VFMADD132SD | VFMADD132SH | VFMADD132SS | VFMADD213PD | VFMADD213PH | VFMADD213PS | VFMADD213SD | VFMADD213SH | VFMADD213SS | VFMADD231PD | VFMADD231PH | VFMADD231PS | VFMADD231SD | VFMADD231SH | VFMADD231SS | VFMADDCPH | VFMADDCSH | VFMADDPD | VFMADDPS | VFMADDSD | VFMADDSS | VFMADDSUB132PD | VFMADDSUB132PH | VFMADDSUB132PS | VFMADDSUB213PD | VFMADDSUB213PH | VFMADDSUB213PS | VFMADDSUB231PD | VFMADDSUB231PH | VFMADDSUB231PS | VFMADDSUBPD | VFMADDSUBPS | VFMSUB132PD | VFMSUB132PH | VFMSUB132PS | VFMSUB132SD | VFMSUB132SH | VFMSUB132SS | VFMSUB213PD | VFMSUB213PH | VFMSUB213PS | VFMSUB213SD | VFMSUB213SH | VFMSUB213SS | VFMSUB231PD | VFMSUB231PH | VFMSUB231PS | VFMSUB231SD | VFMSUB231SH | VFMSUB231SS | VFMSUBADD132PD | VFMSUBADD132PH | VFMSUBADD132PS | VFMSUBADD213PD | VFMSUBADD213PH | VFMSUBADD213PS | VFMSUBADD231PD | VFMSUBADD231PH | VFMSUBADD231PS | VFMSUBADDPD | VFMSUBADDPS | VFMSUBPD | VFMSUBPS | VFMSUBSD | VFMSUBSS | VFMULCPH | VFMULCSH | VFNMADD132PD | VFNMADD132PH | VFNMADD132PS | VFNMADD132SD | VFNMADD132SH | VFNMADD132SS | VFNMADD213PD | VFNMADD213PH | VFNMADD213PS | VFNMADD213SD | VFNMADD213SH | VFNMADD213SS | VFNMADD231PD | VFNMADD231PH | VFNMADD231PS | VFNMADD231SD | VFNMADD231SH | VFNMADD231SS | VFNMADDPD | VFNMADDPS | VFNMADDSD | VFNMADDSS | VFNMSUB132PD | VFNMSUB132PH | VFNMSUB132PS | VFNMSUB132SD | VFNMSUB132SH | VFNMSUB132SS | VFNMSUB213PD | VFNMSUB213PH | VFNMSUB213PS | VFNMSUB213SD | VFNMSUB213SH | VFNMSUB213SS | VFNMSUB231PD | VFNMSUB231PH | VFNMSUB231PS | VFNMSUB231SD | VFNMSUB231SH | VFNMSUB231SS | VFNMSUBPD | VFNMSUBPS | VFNMSUBSD | VFNMSUBSS | VFPCLASSPD | VFPCLASSPH | VFPCLASSPS | VFPCLASSSD | VFPCLASSSH | VFPCLASSSS | VFRCZPD | VFRCZPS | VFRCZSD | VFRCZSS | VGATHERDPD | VGATHERDPS | VGATHERPF0DPD | VGATHERPF0DPS | VGATHERPF0QPD | VGATHERPF0QPS | VGATHERPF1DPD | VGATHERPF1DPS | VGATHERPF1QPD | VGATHERPF1QPS | VGATHERQPD | VGATHERQPS | VGETEXPPD | VGETEXPPH | VGETEXPPS | VGETEXPSD | VGETEXPSH | VGETEXPSS | VGETMANTPD | VGETMANTPH | VGETMANTPS | VGETMANTSD | VGETMANTSH | VGETMANTSS | VGF2P8AFFINEINVQB | VGF2P8AFFINEQB | VGF2P8MULB | VHADDPD | VHADDPS | VHSUBPD | VHSUBPS | VINSERTF128 | VINSERTF32X4 | VINSERTF32X8 | VINSERTF64X2 | VINSERTF64X4 | VINSERTI128 | VINSERTI32X4 | VINSERTI32X8 | VINSERTI64X2 | VINSERTI64X4 | VINSERTPS | VLDDQU | VLDMXCSR | VMASKMOVDQU | VMASKMOVPD | VMASKMOVPS | VMAXPD | VMAXPH | VMAXPS | VMAXSD | VMAXSH | VMAXSS | VMCALL | VMCLEAR | VMFUNC | VMINPD | VMINPH | VMINPS | VMINSD | VMINSH | VMINSS | VMLAUNCH | VMLOAD | VMMCALL | VMOVAPD | VMOVAPS | VMOVD | VMOVDDUP | VMOVDQA | VMOVDQA32 | VMOVDQA64 | VMOVDQU | VMOVDQU16 | VMOVDQU32 | VMOVDQU64 | VMOVDQU8 | VMOVHLPS | VMOVHPD | VMOVHPS | VMOVLHPS | VMOVLPD | VMOVLPS | VMOVMSKPD | VMOVMSKPS | VMOVNTDQ | VMOVNTDQA | VMOVNTPD | VMOVNTPS | VMOVQ | VMOVSD | VMOVSH | VMOVSHDUP | VMOVSLDUP | VMOVSS | VMOVUPD | VMOVUPS | VMOVW | VMPSADBW | VMPTRLD | VMPTRST | VMREAD | VMRESUME | VMRUN | VMSAVE | VMULPD | VMULPH | VMULPS | VMULSD | VMULSH | VMULSS | VMWRITE | VMXOFF | VMXON | VORPD | VORPS | VP2INTERSECTD | VP2INTERSECTQ | VP4DPWSSD | VP4DPWSSDS | VPABSB | VPABSD | VPABSQ | VPABSW | VPACKSSDW | VPACKSSWB | VPACKUSDW | VPACKUSWB | VPADDB | VPADDD | VPADDQ | VPADDSB | VPADDSW | VPADDUSB | VPADDUSW | VPADDW | VPALIGNR | VPAND | VPANDD | VPANDN | VPANDND | VPANDNQ | VPANDQ | VPAVGB | VPAVGW | VPBLENDD | VPBLENDMB | VPBLENDMD | VPBLENDMQ | VPBLENDMW | VPBLENDVB | VPBLENDW | VPBROADCASTB | VPBROADCASTD | VPBROADCASTMB2Q | VPBROADCASTMW2D | VPBROADCASTQ | VPBROADCASTW | VPCLMULQDQ | VPCMOV | VPCMPB | VPCMPD | VPCMPEQB | VPCMPEQD | VPCMPEQQ | VPCMPEQW | VPCMPESTRI | VPCMPESTRI64 | VPCMPESTRM | VPCMPESTRM64 | VPCMPGTB | VPCMPGTD | VPCMPGTQ | VPCMPGTW | VPCMPISTRI | VPCMPISTRI64 | VPCMPISTRM | VPCMPQ | VPCMPUB | VPCMPUD | VPCMPUQ | VPCMPUW | VPCMPW | VPCOMB | VPCOMD | VPCOMPRESSB | VPCOMPRESSD | VPCOMPRESSQ | VPCOMPRESSW | VPCOMQ | VPCOMUB | VPCOMUD | VPCOMUQ | VPCOMUW | VPCOMW | VPCONFLICTD | VPCONFLICTQ | VPDPBSSD | VPDPBSSDS | VPDPBSUD | VPDPBSUDS | VPDPBUSD | VPDPBUSDS | VPDPBUUD | VPDPBUUDS | VPDPWSSD | VPDPWSSDS | VPDPWSUD | VPDPWSUDS | VPDPWUSD | VPDPWUSDS | VPDPWUUD | VPDPWUUDS | VPERM2F128 | VPERM2I128 | VPERMB | VPERMD | VPERMI2B | VPERMI2D | VPERMI2PD | VPERMI2PS | VPERMI2Q | VPERMI2W | VPERMIL2PD | VPERMIL2PS | VPERMILPD | VPERMILPS | VPERMPD | VPERMPS | VPERMQ | VPERMT2B | VPERMT2D | VPERMT2PD | VPERMT2PS | VPERMT2Q | VPERMT2W | VPERMW | VPEXPANDB | VPEXPANDD | VPEXPANDQ | VPEXPANDW | VPEXTRB | VPEXTRD | VPEXTRQ | VPEXTRW | VPEXTRW_C5 | VPGATHERDD | VPGATHERDQ | VPGATHERQD | VPGATHERQQ | VPHADDBD | VPHADDBQ | VPHADDBW | VPHADDD | VPHADDDQ | VPHADDSW | VPHADDUBD | VPHADDUBQ | VPHADDUBW | VPHADDUDQ | VPHADDUWD | VPHADDUWQ | VPHADDW | VPHADDWD | VPHADDWQ | VPHMINPOSUW | VPHSUBBW | VPHSUBD | VPHSUBDQ | VPHSUBSW | VPHSUBW | VPHSUBWD | VPINSRB | VPINSRD | VPINSRQ | VPINSRW | VPLZCNTD | VPLZCNTQ | VPMACSDD | VPMACSDQH | VPMACSDQL | VPMACSSDD | VPMACSSDQH | VPMACSSDQL | VPMACSSWD | VPMACSSWW | VPMACSWD | VPMACSWW | VPMADCSSWD | VPMADCSWD | VPMADD52HUQ | VPMADD52LUQ | VPMADDUBSW | VPMADDWD | VPMASKMOVD | VPMASKMOVQ | VPMAXSB | VPMAXSD | VPMAXSQ | VPMAXSW | VPMAXUB | VPMAXUD | VPMAXUQ | VPMAXUW | VPMINSB | VPMINSD | VPMINSQ | VPMINSW | VPMINUB | VPMINUD | VPMINUQ | VPMINUW | VPMOVB2M | VPMOVD2M | VPMOVDB | VPMOVDW | VPMOVM2B | VPMOVM2D | VPMOVM2Q | VPMOVM2W | VPMOVMSKB | VPMOVQ2M | VPMOVQB | VPMOVQD | VPMOVQW | VPMOVSDB | VPMOVSDW | VPMOVSQB | VPMOVSQD | VPMOVSQW | VPMOVSWB | VPMOVSXBD | VPMOVSXBQ | VPMOVSXBW | VPMOVSXDQ | VPMOVSXWD | VPMOVSXWQ | VPMOVUSDB | VPMOVUSDW | VPMOVUSQB | VPMOVUSQD | VPMOVUSQW | VPMOVUSWB | VPMOVW2M | VPMOVWB | VPMOVZXBD | VPMOVZXBQ | VPMOVZXBW | VPMOVZXDQ | VPMOVZXWD | VPMOVZXWQ | VPMULDQ | VPMULHRSW | VPMULHUW | VPMULHW | VPMULLD | VPMULLQ | VPMULLW | VPMULTISHIFTQB | VPMULUDQ | VPOPCNTB | VPOPCNTD | VPOPCNTQ | VPOPCNTW | VPOR | VPORD | VPORQ | VPPERM | VPROLD | VPROLQ | VPROLVD | VPROLVQ | VPRORD | VPRORQ | VPRORVD | VPRORVQ | VPROTB | VPROTD | VPROTQ | VPROTW | VPSADBW | VPSCATTERDD | VPSCATTERDQ | VPSCATTERQD | VPSCATTERQQ | VPSHAB | VPSHAD | VPSHAQ | VPSHAW | VPSHLB | VPSHLD | VPSHLDD | VPSHLDQ | VPSHLDVD | VPSHLDVQ | VPSHLDVW | VPSHLDW | VPSHLQ | VPSHLW | VPSHRDD | VPSHRDQ | VPSHRDVD | VPSHRDVQ | VPSHRDVW | VPSHRDW | VPSHUFB | VPSHUFBITQMB | VPSHUFD | VPSHUFHW | VPSHUFLW | VPSIGNB | VPSIGND | VPSIGNW | VPSLLD | VPSLLDQ | VPSLLQ | VPSLLVD | VPSLLVQ | VPSLLVW | VPSLLW | VPSRAD | VPSRAQ | VPSRAVD | VPSRAVQ | VPSRAVW | VPSRAW | VPSRLD | VPSRLDQ | VPSRLQ | VPSRLVD | VPSRLVQ | VPSRLVW | VPSRLW | VPSUBB | VPSUBD | VPSUBQ | VPSUBSB | VPSUBSW | VPSUBUSB | VPSUBUSW | VPSUBW | VPTERNLOGD | VPTERNLOGQ | VPTEST | VPTESTMB | VPTESTMD | VPTESTMQ | VPTESTMW | VPTESTNMB | VPTESTNMD | VPTESTNMQ | VPTESTNMW | VPUNPCKHBW | VPUNPCKHDQ | VPUNPCKHQDQ | VPUNPCKHWD | VPUNPCKLBW | VPUNPCKLDQ | VPUNPCKLQDQ | VPUNPCKLWD | VPXOR | VPXORD | VPXORQ | VRANGEPD | VRANGEPS | VRANGESD | VRANGESS | VRCP14PD | VRCP14PS | VRCP14SD | VRCP14SS | VRCP28PD | VRCP28PS | VRCP28SD | VRCP28SS | VRCPPH | VRCPPS | VRCPSH | VRCPSS | VREDUCEPD | VREDUCEPH | VREDUCEPS | VREDUCESD | VREDUCESH | VREDUCESS | VRNDSCALEPD | VRNDSCALEPH | VRNDSCALEPS | VRNDSCALESD | VRNDSCALESH | VRNDSCALESS | VROUNDPD | VROUNDPS | VROUNDSD | VROUNDSS | VRSQRT14PD | VRSQRT14PS | VRSQRT14SD | VRSQRT14SS | VRSQRT28PD | VRSQRT28PS | VRSQRT28SD | VRSQRT28SS | VRSQRTPH | VRSQRTPS | VRSQRTSH | VRSQRTSS | VSCALEFPD | VSCALEFPH | VSCALEFPS | VSCALEFSD | VSCALEFSH | VSCALEFSS | VSCATTERDPD | VSCATTERDPS | VSCATTERPF0DPD | VSCATTERPF0DPS | VSCATTERPF0QPD | VSCATTERPF0QPS | VSCATTERPF1DPD | VSCATTERPF1DPS | VSCATTERPF1QPD | VSCATTERPF1QPS | VSCATTERQPD | VSCATTERQPS | VSHA512MSG1 | VSHA512MSG2 | VSHA512RNDS2 | VSHUFF32X4 | VSHUFF64X2 | VSHUFI32X4 | VSHUFI64X2 | VSHUFPD | VSHUFPS | VSM3MSG1 | VSM3MSG2 | VSM3RNDS2 | VSM4KEY4 | VSM4RNDS4 | VSQRTPD | VSQRTPH | VSQRTPS | VSQRTSD | VSQRTSH | VSQRTSS | VSTMXCSR | VSUBPD | VSUBPH | VSUBPS | VSUBSD | VSUBSH | VSUBSS | VTESTPD | VTESTPS | VUCOMISD | VUCOMISH | VUCOMISS | VUNPCKHPD | VUNPCKHPS | VUNPCKLPD | VUNPCKLPS | VXORPD | VXORPS | VZEROALL | VZEROUPPER | WBINVD | WBNOINVD | WRFSBASE | WRGSBASE | WRMSR | WRMSRLIST | WRMSRNS | WRPKRU | WRSSD | WRSSQ | WRUSSD | WRUSSQ | XABORT | XADD | XADD_LOCK | XBEGIN | XCHG | XEND | XGETBV | XLAT | XOR | XORPD | XORPS | XOR_LOCK | XRESLDTRK | XRSTOR | XRSTOR64 | XRSTORS | XRSTORS64 | XSAVE | XSAVE64 | XSAVEC | XSAVEC64 | XSAVEOPT | XSAVEOPT64 | XSAVES | XSAVES64 | XSETBV | XSTORE | XSUSLDTRK | XTEST let iclass_len = 1859 let iclass_to_int : iclass -> int = Obj.magic let iclass_of_int (x : int) : iclass = if 0 <= x && x < 1859 then Obj.magic x else failwith "iclass_of_int: no enum for given int" type iexception = | INVALID | AMX_E1 | AMX_E1_EVEX | AMX_E2 | AMX_E2_EVEX | AMX_E3 | AMX_E3_EVEX | AMX_E4 | AMX_E5 | AMX_E6 | APX_EVEX_BMI | APX_EVEX_CCMP | APX_EVEX_CET_WRSS | APX_EVEX_CET_WRUSS | APX_EVEX_CFCMOV | APX_EVEX_CMPCCXADD | APX_EVEX_ENQCMD | APX_EVEX_INT | APX_EVEX_INVEPT | APX_EVEX_INVPCID | APX_EVEX_INVVPID | APX_EVEX_KMOV | APX_EVEX_PP2 | APX_EVEX_RAO_INT | APX_LEGACY_JMPABS | AVX512_E1 | AVX512_E10 | AVX512_E10NF | AVX512_E11 | AVX512_E12 | AVX512_E12NP | AVX512_E1NF | AVX512_E2 | AVX512_E3 | AVX512_E3NF | AVX512_E4 | AVX512_E4NF | AVX512_E5 | AVX512_E5NF | AVX512_E6 | AVX512_E6NF | AVX512_E7NM | AVX512_E7NM128 | AVX512_E9NF | AVX512_K20 | AVX512_K21 | AVX_TYPE_1 | AVX_TYPE_11 | AVX_TYPE_12 | AVX_TYPE_14 | AVX_TYPE_2 | AVX_TYPE_2D | AVX_TYPE_3 | AVX_TYPE_4 | AVX_TYPE_4M | AVX_TYPE_5 | AVX_TYPE_5L | AVX_TYPE_6 | AVX_TYPE_7 | AVX_TYPE_8 | LEGACY_RAO_INT | MMX_FP | MMX_FP_16ALIGN | MMX_MEM | MMX_NOFP | MMX_NOFP2 | MMX_NOMEM | SSE_TYPE_1 | SSE_TYPE_2 | SSE_TYPE_2D | SSE_TYPE_3 | SSE_TYPE_4 | SSE_TYPE_4M | SSE_TYPE_5 | SSE_TYPE_7 | USER_MSR_EVEX | USER_MSR_LEGACY | USER_MSR_VEX let iexception_len = 78 let iexception_to_int : iexception -> int = Obj.magic let iexception_of_int (x : int) : iexception = if 0 <= x && x < 78 then Obj.magic x else failwith "iexception_of_int: no enum for given int" type iform = | INVALID | AAA | AAD_IMMb | AADD_MEM32_GPR32 | AADD_MEM64_GPR64 | AADD_MEMi32_GPR32i32_APX | AADD_MEMi64_GPR64i64_APX | AAM_IMMb | AAND_MEM32_GPR32 | AAND_MEM64_GPR64 | AAND_MEMi32_GPR32i32_APX | AAND_MEMi64_GPR64i64_APX | AAS | ADC_AL_IMMb | ADC_GPR8_GPR8_10 | ADC_GPR8_GPR8_12 | ADC_GPR8_IMMb_80r2 | ADC_GPR8_IMMb_82r2 | ADC_GPR8_MEMb | ADC_GPR8i8_GPR8i8_APX | ADC_GPR8i8_GPR8i8_GPR8i8_APX | ADC_GPR8i8_GPR8i8_IMM8_APX | ADC_GPR8i8_GPR8i8_MEMi8_APX | ADC_GPR8i8_IMM8_APX | ADC_GPR8i8_MEMi8_APX | ADC_GPR8i8_MEMi8_GPR8i8_APX | ADC_GPR8i8_MEMi8_IMM8_APX | ADC_GPRv_GPRv_11 | ADC_GPRv_GPRv_13 | ADC_GPRv_GPRv_APX | ADC_GPRv_GPRv_GPRv_APX | ADC_GPRv_GPRv_IMM8_APX | ADC_GPRv_GPRv_IMMz_APX | ADC_GPRv_GPRv_MEMv_APX | ADC_GPRv_IMM8_APX | ADC_GPRv_IMMb | ADC_GPRv_IMMz | ADC_GPRv_IMMz_APX | ADC_GPRv_MEMv | ADC_GPRv_MEMv_APX | ADC_GPRv_MEMv_GPRv_APX | ADC_GPRv_MEMv_IMM8_APX | ADC_GPRv_MEMv_IMMz_APX | ADC_MEMb_GPR8 | ADC_MEMb_IMMb_80r2 | ADC_MEMb_IMMb_82r2 | ADC_MEMi8_GPR8i8_APX | ADC_MEMi8_IMM8_APX | ADC_MEMv_GPRv | ADC_MEMv_GPRv_APX | ADC_MEMv_IMM8_APX | ADC_MEMv_IMMb | ADC_MEMv_IMMz | ADC_MEMv_IMMz_APX | ADC_OrAX_IMMz | ADCX_GPR32d_GPR32d | ADCX_GPR32d_MEMd | ADCX_GPR32i32_GPR32i32_APX | ADCX_GPR32i32_GPR32i32_GPR32i32_APX | ADCX_GPR32i32_GPR32i32_MEMi32_APX | ADCX_GPR32i32_MEMi32_APX | ADCX_GPR64i64_GPR64i64_APX | ADCX_GPR64i64_GPR64i64_GPR64i64_APX | ADCX_GPR64i64_GPR64i64_MEMi64_APX | ADCX_GPR64i64_MEMi64_APX | ADCX_GPR64q_GPR64q | ADCX_GPR64q_MEMq | ADC_LOCK_MEMb_GPR8 | ADC_LOCK_MEMb_IMMb_80r2 | ADC_LOCK_MEMb_IMMb_82r2 | ADC_LOCK_MEMv_GPRv | ADC_LOCK_MEMv_IMMb | ADC_LOCK_MEMv_IMMz | ADD_AL_IMMb | ADD_GPR8_GPR8_00 | ADD_GPR8_GPR8_02 | ADD_GPR8_IMMb_80r0 | ADD_GPR8_IMMb_82r0 | ADD_GPR8_MEMb | ADD_GPR8i8_GPR8i8_APX | ADD_GPR8i8_GPR8i8_GPR8i8_APX | ADD_GPR8i8_GPR8i8_IMM8_APX | ADD_GPR8i8_GPR8i8_MEMi8_APX | ADD_GPR8i8_IMM8_APX | ADD_GPR8i8_MEMi8_APX | ADD_GPR8i8_MEMi8_GPR8i8_APX | ADD_GPR8i8_MEMi8_IMM8_APX | ADD_GPRv_GPRv_01 | ADD_GPRv_GPRv_03 | ADD_GPRv_GPRv_APX | ADD_GPRv_GPRv_GPRv_APX | ADD_GPRv_GPRv_IMM8_APX | ADD_GPRv_GPRv_IMMz_APX | ADD_GPRv_GPRv_MEMv_APX | ADD_GPRv_IMM8_APX | ADD_GPRv_IMMb | ADD_GPRv_IMMz | ADD_GPRv_IMMz_APX | ADD_GPRv_MEMv | ADD_GPRv_MEMv_APX | ADD_GPRv_MEMv_GPRv_APX | ADD_GPRv_MEMv_IMM8_APX | ADD_GPRv_MEMv_IMMz_APX | ADD_MEMb_GPR8 | ADD_MEMb_IMMb_80r0 | ADD_MEMb_IMMb_82r0 | ADD_MEMi8_GPR8i8_APX | ADD_MEMi8_IMM8_APX | ADD_MEMv_GPRv | ADD_MEMv_GPRv_APX | ADD_MEMv_IMM8_APX | ADD_MEMv_IMMb | ADD_MEMv_IMMz | ADD_MEMv_IMMz_APX | ADD_OrAX_IMMz | ADDPD_XMMpd_MEMpd | ADDPD_XMMpd_XMMpd | ADDPS_XMMps_MEMps | ADDPS_XMMps_XMMps | ADDSD_XMMsd_MEMsd | ADDSD_XMMsd_XMMsd | ADDSS_XMMss_MEMss | ADDSS_XMMss_XMMss | ADDSUBPD_XMMpd_MEMpd | ADDSUBPD_XMMpd_XMMpd | ADDSUBPS_XMMps_MEMps | ADDSUBPS_XMMps_XMMps | ADD_LOCK_MEMb_GPR8 | ADD_LOCK_MEMb_IMMb_80r0 | ADD_LOCK_MEMb_IMMb_82r0 | ADD_LOCK_MEMv_GPRv | ADD_LOCK_MEMv_IMMb | ADD_LOCK_MEMv_IMMz | ADOX_GPR32d_GPR32d | ADOX_GPR32d_MEMd | ADOX_GPR32i32_GPR32i32_APX | ADOX_GPR32i32_GPR32i32_GPR32i32_APX | ADOX_GPR32i32_GPR32i32_MEMi32_APX | ADOX_GPR32i32_MEMi32_APX | ADOX_GPR64i64_GPR64i64_APX | ADOX_GPR64i64_GPR64i64_GPR64i64_APX | ADOX_GPR64i64_GPR64i64_MEMi64_APX | ADOX_GPR64i64_MEMi64_APX | ADOX_GPR64q_GPR64q | ADOX_GPR64q_MEMq | AESDEC_XMMdq_MEMdq | AESDEC_XMMdq_XMMdq | AESDEC128KL_XMMu8_MEMu8 | AESDEC256KL_XMMu8_MEMu8 | AESDECLAST_XMMdq_MEMdq | AESDECLAST_XMMdq_XMMdq | AESDECWIDE128KL_MEMu8 | AESDECWIDE256KL_MEMu8 | AESENC_XMMdq_MEMdq | AESENC_XMMdq_XMMdq | AESENC128KL_XMMu8_MEMu8 | AESENC256KL_XMMu8_MEMu8 | AESENCLAST_XMMdq_MEMdq | AESENCLAST_XMMdq_XMMdq | AESENCWIDE128KL_MEMu8 | AESENCWIDE256KL_MEMu8 | AESIMC_XMMdq_MEMdq | AESIMC_XMMdq_XMMdq | AESKEYGENASSIST_XMMdq_MEMdq_IMMb | AESKEYGENASSIST_XMMdq_XMMdq_IMMb | AND_AL_IMMb | AND_GPR8_GPR8_20 | AND_GPR8_GPR8_22 | AND_GPR8_IMMb_80r4 | AND_GPR8_IMMb_82r4 | AND_GPR8_MEMb | AND_GPR8i8_GPR8i8_APX | AND_GPR8i8_GPR8i8_GPR8i8_APX | AND_GPR8i8_GPR8i8_IMM8_APX | AND_GPR8i8_GPR8i8_MEMi8_APX | AND_GPR8i8_IMM8_APX | AND_GPR8i8_MEMi8_APX | AND_GPR8i8_MEMi8_GPR8i8_APX | AND_GPR8i8_MEMi8_IMM8_APX | AND_GPRv_GPRv_21 | AND_GPRv_GPRv_23 | AND_GPRv_GPRv_APX | AND_GPRv_GPRv_GPRv_APX | AND_GPRv_GPRv_IMM8_APX | AND_GPRv_GPRv_IMMz_APX | AND_GPRv_GPRv_MEMv_APX | AND_GPRv_IMM8_APX | AND_GPRv_IMMb | AND_GPRv_IMMz | AND_GPRv_IMMz_APX | AND_GPRv_MEMv | AND_GPRv_MEMv_APX | AND_GPRv_MEMv_GPRv_APX | AND_GPRv_MEMv_IMM8_APX | AND_GPRv_MEMv_IMMz_APX | AND_MEMb_GPR8 | AND_MEMb_IMMb_80r4 | AND_MEMb_IMMb_82r4 | AND_MEMi8_GPR8i8_APX | AND_MEMi8_IMM8_APX | AND_MEMv_GPRv | AND_MEMv_GPRv_APX | AND_MEMv_IMM8_APX | AND_MEMv_IMMb | AND_MEMv_IMMz | AND_MEMv_IMMz_APX | AND_OrAX_IMMz | ANDN_GPR32d_GPR32d_GPR32d | ANDN_GPR32d_GPR32d_MEMd | ANDN_GPR32i32_GPR32i32_GPR32i32_APX | ANDN_GPR32i32_GPR32i32_MEMi32_APX | ANDN_GPR64i64_GPR64i64_GPR64i64_APX | ANDN_GPR64i64_GPR64i64_MEMi64_APX | ANDN_GPR64q_GPR64q_GPR64q | ANDN_GPR64q_GPR64q_MEMq | ANDNPD_XMMxuq_MEMxuq | ANDNPD_XMMxuq_XMMxuq | ANDNPS_XMMxud_MEMxud | ANDNPS_XMMxud_XMMxud | ANDPD_XMMxuq_MEMxuq | ANDPD_XMMxuq_XMMxuq | ANDPS_XMMxud_MEMxud | ANDPS_XMMxud_XMMxud | AND_LOCK_MEMb_GPR8 | AND_LOCK_MEMb_IMMb_80r4 | AND_LOCK_MEMb_IMMb_82r4 | AND_LOCK_MEMv_GPRv | AND_LOCK_MEMv_IMMb | AND_LOCK_MEMv_IMMz | AOR_MEM32_GPR32 | AOR_MEM64_GPR64 | AOR_MEMi32_GPR32i32_APX | AOR_MEMi64_GPR64i64_APX | ARPL_GPR16_GPR16 | ARPL_MEMw_GPR16 | AXOR_MEM32_GPR32 | AXOR_MEM64_GPR64 | AXOR_MEMi32_GPR32i32_APX | AXOR_MEMi64_GPR64i64_APX | BEXTR_GPR32d_GPR32d_GPR32d | BEXTR_GPR32d_MEMd_GPR32d | BEXTR_GPR32i32_GPR32i32_GPR32i32_APX | BEXTR_GPR32i32_MEMi32_GPR32i32_APX | BEXTR_GPR64i64_GPR64i64_GPR64i64_APX | BEXTR_GPR64i64_MEMi64_GPR64i64_APX | BEXTR_GPR64q_GPR64q_GPR64q | BEXTR_GPR64q_MEMq_GPR64q | BEXTR_XOP_GPR32d_GPR32d_IMMd | BEXTR_XOP_GPR32d_MEMd_IMMd | BEXTR_XOP_GPRyy_GPRyy_IMMd | BEXTR_XOP_GPRyy_MEMy_IMMd | BLCFILL_GPR32d_GPR32d | BLCFILL_GPR32d_MEMd | BLCFILL_GPRyy_GPRyy | BLCFILL_GPRyy_MEMy | BLCI_GPR32d_GPR32d | BLCI_GPR32d_MEMd | BLCI_GPRyy_GPRyy | BLCI_GPRyy_MEMy | BLCIC_GPR32d_GPR32d | BLCIC_GPR32d_MEMd | BLCIC_GPRyy_GPRyy | BLCIC_GPRyy_MEMy | BLCMSK_GPR32d_GPR32d | BLCMSK_GPR32d_MEMd | BLCMSK_GPRyy_GPRyy | BLCMSK_GPRyy_MEMy | BLCS_GPR32d_GPR32d | BLCS_GPR32d_MEMd | BLCS_GPRyy_GPRyy | BLCS_GPRyy_MEMy | BLENDPD_XMMdq_MEMdq_IMMb | BLENDPD_XMMdq_XMMdq_IMMb | BLENDPS_XMMdq_MEMdq_IMMb | BLENDPS_XMMdq_XMMdq_IMMb | BLENDVPD_XMMdq_MEMdq | BLENDVPD_XMMdq_XMMdq | BLENDVPS_XMMdq_MEMdq | BLENDVPS_XMMdq_XMMdq | BLSFILL_GPR32d_GPR32d | BLSFILL_GPR32d_MEMd | BLSFILL_GPRyy_GPRyy | BLSFILL_GPRyy_MEMy | BLSI_GPR32d_GPR32d | BLSI_GPR32d_MEMd | BLSI_GPR32i32_GPR32i32_APX | BLSI_GPR32i32_MEMi32_APX | BLSI_GPR64i64_GPR64i64_APX | BLSI_GPR64i64_MEMi64_APX | BLSI_GPR64q_GPR64q | BLSI_GPR64q_MEMq | BLSIC_GPR32d_GPR32d | BLSIC_GPR32d_MEMd | BLSIC_GPRyy_GPRyy | BLSIC_GPRyy_MEMy | BLSMSK_GPR32d_GPR32d | BLSMSK_GPR32d_MEMd | BLSMSK_GPR32i32_GPR32i32_APX | BLSMSK_GPR32i32_MEMi32_APX | BLSMSK_GPR64i64_GPR64i64_APX | BLSMSK_GPR64i64_MEMi64_APX | BLSMSK_GPR64q_GPR64q | BLSMSK_GPR64q_MEMq | BLSR_GPR32d_GPR32d | BLSR_GPR32d_MEMd | BLSR_GPR32i32_GPR32i32_APX | BLSR_GPR32i32_MEMi32_APX | BLSR_GPR64i64_GPR64i64_APX | BLSR_GPR64i64_MEMi64_APX | BLSR_GPR64q_GPR64q | BLSR_GPR64q_MEMq | BNDCL_BND_AGEN | BNDCL_BND_GPR32 | BNDCL_BND_GPR64 | BNDCN_BND_AGEN | BNDCN_BND_GPR32 | BNDCN_BND_GPR64 | BNDCU_BND_AGEN | BNDCU_BND_GPR32 | BNDCU_BND_GPR64 | BNDLDX_BND_MEMbnd32 | BNDLDX_BND_MEMbnd64 | BNDMK_BND_AGEN | BNDMOV_BND_BND | BNDMOV_BND_MEMdq | BNDMOV_BND_MEMq | BNDMOV_MEMdq_BND | BNDMOV_MEMq_BND | BNDSTX_MEMbnd32_BND | BNDSTX_MEMbnd64_BND | BOUND_GPR16_MEMa16 | BOUND_GPR32_MEMa32 | BSF_GPRv_GPRv | BSF_GPRv_MEMv | BSR_GPRv_GPRv | BSR_GPRv_MEMv | BSWAP_GPRv | BT_GPRv_GPRv | BT_GPRv_IMMb | BT_MEMv_GPRv | BT_MEMv_IMMb | BTC_GPRv_GPRv | BTC_GPRv_IMMb | BTC_MEMv_GPRv | BTC_MEMv_IMMb | BTC_LOCK_MEMv_GPRv | BTC_LOCK_MEMv_IMMb | BTR_GPRv_GPRv | BTR_GPRv_IMMb | BTR_MEMv_GPRv | BTR_MEMv_IMMb | BTR_LOCK_MEMv_GPRv | BTR_LOCK_MEMv_IMMb | BTS_GPRv_GPRv | BTS_GPRv_IMMb | BTS_MEMv_GPRv | BTS_MEMv_IMMb | BTS_LOCK_MEMv_GPRv | BTS_LOCK_MEMv_IMMb | BZHI_GPR32d_GPR32d_GPR32d | BZHI_GPR32d_MEMd_GPR32d | BZHI_GPR32i32_GPR32i32_GPR32i32_APX | BZHI_GPR32i32_MEMi32_GPR32i32_APX | BZHI_GPR64i64_GPR64i64_GPR64i64_APX | BZHI_GPR64i64_MEMi64_GPR64i64_APX | BZHI_GPR64q_GPR64q_GPR64q | BZHI_GPR64q_MEMq_GPR64q | CALL_FAR_MEMp2 | CALL_FAR_PTRp_IMMw | CALL_NEAR_GPRv | CALL_NEAR_MEMv | CALL_NEAR_RELBRd | CALL_NEAR_RELBRz | CBW | CCMPB_GPR8i8_GPR8i8_DFV_APX | CCMPB_GPR8i8_IMM8_DFV_APX | CCMPB_GPR8i8_MEMi8_DFV_APX | CCMPB_GPRv_GPRv_DFV_APX | CCMPB_GPRv_IMM8_DFV_APX | CCMPB_GPRv_IMMz_DFV_APX | CCMPB_GPRv_MEMv_DFV_APX | CCMPB_MEMi8_GPR8i8_DFV_APX | CCMPB_MEMi8_IMM8_DFV_APX | CCMPB_MEMv_GPRv_DFV_APX | CCMPB_MEMv_IMM8_DFV_APX | CCMPB_MEMv_IMMz_DFV_APX | CCMPBE_GPR8i8_GPR8i8_DFV_APX | CCMPBE_GPR8i8_IMM8_DFV_APX | CCMPBE_GPR8i8_MEMi8_DFV_APX | CCMPBE_GPRv_GPRv_DFV_APX | CCMPBE_GPRv_IMM8_DFV_APX | CCMPBE_GPRv_IMMz_DFV_APX | CCMPBE_GPRv_MEMv_DFV_APX | CCMPBE_MEMi8_GPR8i8_DFV_APX | CCMPBE_MEMi8_IMM8_DFV_APX | CCMPBE_MEMv_GPRv_DFV_APX | CCMPBE_MEMv_IMM8_DFV_APX | CCMPBE_MEMv_IMMz_DFV_APX | CCMPF_GPR8i8_GPR8i8_DFV_APX | CCMPF_GPR8i8_IMM8_DFV_APX | CCMPF_GPR8i8_MEMi8_DFV_APX | CCMPF_GPRv_GPRv_DFV_APX | CCMPF_GPRv_IMM8_DFV_APX | CCMPF_GPRv_IMMz_DFV_APX | CCMPF_GPRv_MEMv_DFV_APX | CCMPF_MEMi8_GPR8i8_DFV_APX | CCMPF_MEMi8_IMM8_DFV_APX | CCMPF_MEMv_GPRv_DFV_APX | CCMPF_MEMv_IMM8_DFV_APX | CCMPF_MEMv_IMMz_DFV_APX | CCMPL_GPR8i8_GPR8i8_DFV_APX | CCMPL_GPR8i8_IMM8_DFV_APX | CCMPL_GPR8i8_MEMi8_DFV_APX | CCMPL_GPRv_GPRv_DFV_APX | CCMPL_GPRv_IMM8_DFV_APX | CCMPL_GPRv_IMMz_DFV_APX | CCMPL_GPRv_MEMv_DFV_APX | CCMPL_MEMi8_GPR8i8_DFV_APX | CCMPL_MEMi8_IMM8_DFV_APX | CCMPL_MEMv_GPRv_DFV_APX | CCMPL_MEMv_IMM8_DFV_APX | CCMPL_MEMv_IMMz_DFV_APX | CCMPLE_GPR8i8_GPR8i8_DFV_APX | CCMPLE_GPR8i8_IMM8_DFV_APX | CCMPLE_GPR8i8_MEMi8_DFV_APX | CCMPLE_GPRv_GPRv_DFV_APX | CCMPLE_GPRv_IMM8_DFV_APX | CCMPLE_GPRv_IMMz_DFV_APX | CCMPLE_GPRv_MEMv_DFV_APX | CCMPLE_MEMi8_GPR8i8_DFV_APX | CCMPLE_MEMi8_IMM8_DFV_APX | CCMPLE_MEMv_GPRv_DFV_APX | CCMPLE_MEMv_IMM8_DFV_APX | CCMPLE_MEMv_IMMz_DFV_APX | CCMPNB_GPR8i8_GPR8i8_DFV_APX | CCMPNB_GPR8i8_IMM8_DFV_APX | CCMPNB_GPR8i8_MEMi8_DFV_APX | CCMPNB_GPRv_GPRv_DFV_APX | CCMPNB_GPRv_IMM8_DFV_APX | CCMPNB_GPRv_IMMz_DFV_APX | CCMPNB_GPRv_MEMv_DFV_APX | CCMPNB_MEMi8_GPR8i8_DFV_APX | CCMPNB_MEMi8_IMM8_DFV_APX | CCMPNB_MEMv_GPRv_DFV_APX | CCMPNB_MEMv_IMM8_DFV_APX | CCMPNB_MEMv_IMMz_DFV_APX | CCMPNBE_GPR8i8_GPR8i8_DFV_APX | CCMPNBE_GPR8i8_IMM8_DFV_APX | CCMPNBE_GPR8i8_MEMi8_DFV_APX | CCMPNBE_GPRv_GPRv_DFV_APX | CCMPNBE_GPRv_IMM8_DFV_APX | CCMPNBE_GPRv_IMMz_DFV_APX | CCMPNBE_GPRv_MEMv_DFV_APX | CCMPNBE_MEMi8_GPR8i8_DFV_APX | CCMPNBE_MEMi8_IMM8_DFV_APX | CCMPNBE_MEMv_GPRv_DFV_APX | CCMPNBE_MEMv_IMM8_DFV_APX | CCMPNBE_MEMv_IMMz_DFV_APX | CCMPNL_GPR8i8_GPR8i8_DFV_APX | CCMPNL_GPR8i8_IMM8_DFV_APX | CCMPNL_GPR8i8_MEMi8_DFV_APX | CCMPNL_GPRv_GPRv_DFV_APX | CCMPNL_GPRv_IMM8_DFV_APX | CCMPNL_GPRv_IMMz_DFV_APX | CCMPNL_GPRv_MEMv_DFV_APX | CCMPNL_MEMi8_GPR8i8_DFV_APX | CCMPNL_MEMi8_IMM8_DFV_APX | CCMPNL_MEMv_GPRv_DFV_APX | CCMPNL_MEMv_IMM8_DFV_APX | CCMPNL_MEMv_IMMz_DFV_APX | CCMPNLE_GPR8i8_GPR8i8_DFV_APX | CCMPNLE_GPR8i8_IMM8_DFV_APX | CCMPNLE_GPR8i8_MEMi8_DFV_APX | CCMPNLE_GPRv_GPRv_DFV_APX | CCMPNLE_GPRv_IMM8_DFV_APX | CCMPNLE_GPRv_IMMz_DFV_APX | CCMPNLE_GPRv_MEMv_DFV_APX | CCMPNLE_MEMi8_GPR8i8_DFV_APX | CCMPNLE_MEMi8_IMM8_DFV_APX | CCMPNLE_MEMv_GPRv_DFV_APX | CCMPNLE_MEMv_IMM8_DFV_APX | CCMPNLE_MEMv_IMMz_DFV_APX | CCMPNO_GPR8i8_GPR8i8_DFV_APX | CCMPNO_GPR8i8_IMM8_DFV_APX | CCMPNO_GPR8i8_MEMi8_DFV_APX | CCMPNO_GPRv_GPRv_DFV_APX | CCMPNO_GPRv_IMM8_DFV_APX | CCMPNO_GPRv_IMMz_DFV_APX | CCMPNO_GPRv_MEMv_DFV_APX | CCMPNO_MEMi8_GPR8i8_DFV_APX | CCMPNO_MEMi8_IMM8_DFV_APX | CCMPNO_MEMv_GPRv_DFV_APX | CCMPNO_MEMv_IMM8_DFV_APX | CCMPNO_MEMv_IMMz_DFV_APX | CCMPNS_GPR8i8_GPR8i8_DFV_APX | CCMPNS_GPR8i8_IMM8_DFV_APX | CCMPNS_GPR8i8_MEMi8_DFV_APX | CCMPNS_GPRv_GPRv_DFV_APX | CCMPNS_GPRv_IMM8_DFV_APX | CCMPNS_GPRv_IMMz_DFV_APX | CCMPNS_GPRv_MEMv_DFV_APX | CCMPNS_MEMi8_GPR8i8_DFV_APX | CCMPNS_MEMi8_IMM8_DFV_APX | CCMPNS_MEMv_GPRv_DFV_APX | CCMPNS_MEMv_IMM8_DFV_APX | CCMPNS_MEMv_IMMz_DFV_APX | CCMPNZ_GPR8i8_GPR8i8_DFV_APX | CCMPNZ_GPR8i8_IMM8_DFV_APX | CCMPNZ_GPR8i8_MEMi8_DFV_APX | CCMPNZ_GPRv_GPRv_DFV_APX | CCMPNZ_GPRv_IMM8_DFV_APX | CCMPNZ_GPRv_IMMz_DFV_APX | CCMPNZ_GPRv_MEMv_DFV_APX | CCMPNZ_MEMi8_GPR8i8_DFV_APX | CCMPNZ_MEMi8_IMM8_DFV_APX | CCMPNZ_MEMv_GPRv_DFV_APX | CCMPNZ_MEMv_IMM8_DFV_APX | CCMPNZ_MEMv_IMMz_DFV_APX | CCMPO_GPR8i8_GPR8i8_DFV_APX | CCMPO_GPR8i8_IMM8_DFV_APX | CCMPO_GPR8i8_MEMi8_DFV_APX | CCMPO_GPRv_GPRv_DFV_APX | CCMPO_GPRv_IMM8_DFV_APX | CCMPO_GPRv_IMMz_DFV_APX | CCMPO_GPRv_MEMv_DFV_APX | CCMPO_MEMi8_GPR8i8_DFV_APX | CCMPO_MEMi8_IMM8_DFV_APX | CCMPO_MEMv_GPRv_DFV_APX | CCMPO_MEMv_IMM8_DFV_APX | CCMPO_MEMv_IMMz_DFV_APX | CCMPS_GPR8i8_GPR8i8_DFV_APX | CCMPS_GPR8i8_IMM8_DFV_APX | CCMPS_GPR8i8_MEMi8_DFV_APX | CCMPS_GPRv_GPRv_DFV_APX | CCMPS_GPRv_IMM8_DFV_APX | CCMPS_GPRv_IMMz_DFV_APX | CCMPS_GPRv_MEMv_DFV_APX | CCMPS_MEMi8_GPR8i8_DFV_APX | CCMPS_MEMi8_IMM8_DFV_APX | CCMPS_MEMv_GPRv_DFV_APX | CCMPS_MEMv_IMM8_DFV_APX | CCMPS_MEMv_IMMz_DFV_APX | CCMPT_GPR8i8_GPR8i8_DFV_APX | CCMPT_GPR8i8_IMM8_DFV_APX | CCMPT_GPR8i8_MEMi8_DFV_APX | CCMPT_GPRv_GPRv_DFV_APX | CCMPT_GPRv_IMM8_DFV_APX | CCMPT_GPRv_IMMz_DFV_APX | CCMPT_GPRv_MEMv_DFV_APX | CCMPT_MEMi8_GPR8i8_DFV_APX | CCMPT_MEMi8_IMM8_DFV_APX | CCMPT_MEMv_GPRv_DFV_APX | CCMPT_MEMv_IMM8_DFV_APX | CCMPT_MEMv_IMMz_DFV_APX | CCMPZ_GPR8i8_GPR8i8_DFV_APX | CCMPZ_GPR8i8_IMM8_DFV_APX | CCMPZ_GPR8i8_MEMi8_DFV_APX | CCMPZ_GPRv_GPRv_DFV_APX | CCMPZ_GPRv_IMM8_DFV_APX | CCMPZ_GPRv_IMMz_DFV_APX | CCMPZ_GPRv_MEMv_DFV_APX | CCMPZ_MEMi8_GPR8i8_DFV_APX | CCMPZ_MEMi8_IMM8_DFV_APX | CCMPZ_MEMv_GPRv_DFV_APX | CCMPZ_MEMv_IMM8_DFV_APX | CCMPZ_MEMv_IMMz_DFV_APX | CDQ | CDQE | CFCMOVB_GPRv_GPRv_APX | CFCMOVB_GPRv_GPRv_GPRv_APX | CFCMOVB_GPRv_GPRv_MEMv_APX | CFCMOVB_GPRv_MEMv_APX | CFCMOVB_MEMv_GPRv_APX | CFCMOVBE_GPRv_GPRv_APX | CFCMOVBE_GPRv_GPRv_GPRv_APX | CFCMOVBE_GPRv_GPRv_MEMv_APX | CFCMOVBE_GPRv_MEMv_APX | CFCMOVBE_MEMv_GPRv_APX | CFCMOVL_GPRv_GPRv_APX | CFCMOVL_GPRv_GPRv_GPRv_APX | CFCMOVL_GPRv_GPRv_MEMv_APX | CFCMOVL_GPRv_MEMv_APX | CFCMOVL_MEMv_GPRv_APX | CFCMOVLE_GPRv_GPRv_APX | CFCMOVLE_GPRv_GPRv_GPRv_APX | CFCMOVLE_GPRv_GPRv_MEMv_APX | CFCMOVLE_GPRv_MEMv_APX | CFCMOVLE_MEMv_GPRv_APX | CFCMOVNB_GPRv_GPRv_APX | CFCMOVNB_GPRv_GPRv_GPRv_APX | CFCMOVNB_GPRv_GPRv_MEMv_APX | CFCMOVNB_GPRv_MEMv_APX | CFCMOVNB_MEMv_GPRv_APX | CFCMOVNBE_GPRv_GPRv_APX | CFCMOVNBE_GPRv_GPRv_GPRv_APX | CFCMOVNBE_GPRv_GPRv_MEMv_APX | CFCMOVNBE_GPRv_MEMv_APX | CFCMOVNBE_MEMv_GPRv_APX | CFCMOVNL_GPRv_GPRv_APX | CFCMOVNL_GPRv_GPRv_GPRv_APX | CFCMOVNL_GPRv_GPRv_MEMv_APX | CFCMOVNL_GPRv_MEMv_APX | CFCMOVNL_MEMv_GPRv_APX | CFCMOVNLE_GPRv_GPRv_APX | CFCMOVNLE_GPRv_GPRv_GPRv_APX | CFCMOVNLE_GPRv_GPRv_MEMv_APX | CFCMOVNLE_GPRv_MEMv_APX | CFCMOVNLE_MEMv_GPRv_APX | CFCMOVNO_GPRv_GPRv_APX | CFCMOVNO_GPRv_GPRv_GPRv_APX | CFCMOVNO_GPRv_GPRv_MEMv_APX | CFCMOVNO_GPRv_MEMv_APX | CFCMOVNO_MEMv_GPRv_APX | CFCMOVNP_GPRv_GPRv_APX | CFCMOVNP_GPRv_GPRv_GPRv_APX | CFCMOVNP_GPRv_GPRv_MEMv_APX | CFCMOVNP_GPRv_MEMv_APX | CFCMOVNP_MEMv_GPRv_APX | CFCMOVNS_GPRv_GPRv_APX | CFCMOVNS_GPRv_GPRv_GPRv_APX | CFCMOVNS_GPRv_GPRv_MEMv_APX | CFCMOVNS_GPRv_MEMv_APX | CFCMOVNS_MEMv_GPRv_APX | CFCMOVNZ_GPRv_GPRv_APX | CFCMOVNZ_GPRv_GPRv_GPRv_APX | CFCMOVNZ_GPRv_GPRv_MEMv_APX | CFCMOVNZ_GPRv_MEMv_APX | CFCMOVNZ_MEMv_GPRv_APX | CFCMOVO_GPRv_GPRv_APX | CFCMOVO_GPRv_GPRv_GPRv_APX | CFCMOVO_GPRv_GPRv_MEMv_APX | CFCMOVO_GPRv_MEMv_APX | CFCMOVO_MEMv_GPRv_APX | CFCMOVP_GPRv_GPRv_APX | CFCMOVP_GPRv_GPRv_GPRv_APX | CFCMOVP_GPRv_GPRv_MEMv_APX | CFCMOVP_GPRv_MEMv_APX | CFCMOVP_MEMv_GPRv_APX | CFCMOVS_GPRv_GPRv_APX | CFCMOVS_GPRv_GPRv_GPRv_APX | CFCMOVS_GPRv_GPRv_MEMv_APX | CFCMOVS_GPRv_MEMv_APX | CFCMOVS_MEMv_GPRv_APX | CFCMOVZ_GPRv_GPRv_APX | CFCMOVZ_GPRv_GPRv_GPRv_APX | CFCMOVZ_GPRv_GPRv_MEMv_APX | CFCMOVZ_GPRv_MEMv_APX | CFCMOVZ_MEMv_GPRv_APX | CLAC | CLC | CLD | CLDEMOTE_MEMu8 | CLFLUSH_MEMmprefetch | CLFLUSHOPT_MEMmprefetch | CLGI | CLI | CLRSSBSY_MEMu64 | CLTS | CLUI | CLWB_MEMmprefetch | CLZERO | CMC | CMOVB_GPRv_GPRv | CMOVB_GPRv_GPRv_GPRv_APX | CMOVB_GPRv_GPRv_MEMv_APX | CMOVB_GPRv_MEMv | CMOVBE_GPRv_GPRv | CMOVBE_GPRv_GPRv_GPRv_APX | CMOVBE_GPRv_GPRv_MEMv_APX | CMOVBE_GPRv_MEMv | CMOVL_GPRv_GPRv | CMOVL_GPRv_GPRv_GPRv_APX | CMOVL_GPRv_GPRv_MEMv_APX | CMOVL_GPRv_MEMv | CMOVLE_GPRv_GPRv | CMOVLE_GPRv_GPRv_GPRv_APX | CMOVLE_GPRv_GPRv_MEMv_APX | CMOVLE_GPRv_MEMv | CMOVNB_GPRv_GPRv | CMOVNB_GPRv_GPRv_GPRv_APX | CMOVNB_GPRv_GPRv_MEMv_APX | CMOVNB_GPRv_MEMv | CMOVNBE_GPRv_GPRv | CMOVNBE_GPRv_GPRv_GPRv_APX | CMOVNBE_GPRv_GPRv_MEMv_APX | CMOVNBE_GPRv_MEMv | CMOVNL_GPRv_GPRv | CMOVNL_GPRv_GPRv_GPRv_APX | CMOVNL_GPRv_GPRv_MEMv_APX | CMOVNL_GPRv_MEMv | CMOVNLE_GPRv_GPRv | CMOVNLE_GPRv_GPRv_GPRv_APX | CMOVNLE_GPRv_GPRv_MEMv_APX | CMOVNLE_GPRv_MEMv | CMOVNO_GPRv_GPRv | CMOVNO_GPRv_GPRv_GPRv_APX | CMOVNO_GPRv_GPRv_MEMv_APX | CMOVNO_GPRv_MEMv | CMOVNP_GPRv_GPRv | CMOVNP_GPRv_GPRv_GPRv_APX | CMOVNP_GPRv_GPRv_MEMv_APX | CMOVNP_GPRv_MEMv | CMOVNS_GPRv_GPRv | CMOVNS_GPRv_GPRv_GPRv_APX | CMOVNS_GPRv_GPRv_MEMv_APX | CMOVNS_GPRv_MEMv | CMOVNZ_GPRv_GPRv | CMOVNZ_GPRv_GPRv_GPRv_APX | CMOVNZ_GPRv_GPRv_MEMv_APX | CMOVNZ_GPRv_MEMv | CMOVO_GPRv_GPRv | CMOVO_GPRv_GPRv_GPRv_APX | CMOVO_GPRv_GPRv_MEMv_APX | CMOVO_GPRv_MEMv | CMOVP_GPRv_GPRv | CMOVP_GPRv_GPRv_GPRv_APX | CMOVP_GPRv_GPRv_MEMv_APX | CMOVP_GPRv_MEMv | CMOVS_GPRv_GPRv | CMOVS_GPRv_GPRv_GPRv_APX | CMOVS_GPRv_GPRv_MEMv_APX | CMOVS_GPRv_MEMv | CMOVZ_GPRv_GPRv | CMOVZ_GPRv_GPRv_GPRv_APX | CMOVZ_GPRv_GPRv_MEMv_APX | CMOVZ_GPRv_MEMv | CMP_AL_IMMb | CMP_GPR8_GPR8_38 | CMP_GPR8_GPR8_3A | CMP_GPR8_IMMb_80r7 | CMP_GPR8_IMMb_82r7 | CMP_GPR8_MEMb | CMP_GPRv_GPRv_39 | CMP_GPRv_GPRv_3B | CMP_GPRv_IMMb | CMP_GPRv_IMMz | CMP_GPRv_MEMv | CMP_MEMb_GPR8 | CMP_MEMb_IMMb_80r7 | CMP_MEMb_IMMb_82r7 | CMP_MEMv_GPRv | CMP_MEMv_IMMb | CMP_MEMv_IMMz | CMP_OrAX_IMMz | CMPBEXADD_MEMu32_GPR32u32_GPR32u32 | CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPBEXADD_MEMu64_GPR64u64_GPR64u64 | CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPBXADD_MEMu32_GPR32u32_GPR32u32 | CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPBXADD_MEMu64_GPR64u64_GPR64u64 | CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPLEXADD_MEMu32_GPR32u32_GPR32u32 | CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPLEXADD_MEMu64_GPR64u64_GPR64u64 | CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPLXADD_MEMu32_GPR32u32_GPR32u32 | CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPLXADD_MEMu64_GPR64u64_GPR64u64 | CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNBEXADD_MEMu32_GPR32u32_GPR32u32 | CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNBEXADD_MEMu64_GPR64u64_GPR64u64 | CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNBXADD_MEMu32_GPR32u32_GPR32u32 | CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNBXADD_MEMu64_GPR64u64_GPR64u64 | CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNLEXADD_MEMu32_GPR32u32_GPR32u32 | CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNLEXADD_MEMu64_GPR64u64_GPR64u64 | CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNLXADD_MEMu32_GPR32u32_GPR32u32 | CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNLXADD_MEMu64_GPR64u64_GPR64u64 | CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNOXADD_MEMu32_GPR32u32_GPR32u32 | CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNOXADD_MEMu64_GPR64u64_GPR64u64 | CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNPXADD_MEMu32_GPR32u32_GPR32u32 | CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNPXADD_MEMu64_GPR64u64_GPR64u64 | CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNSXADD_MEMu32_GPR32u32_GPR32u32 | CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNSXADD_MEMu64_GPR64u64_GPR64u64 | CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPNZXADD_MEMu32_GPR32u32_GPR32u32 | CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPNZXADD_MEMu64_GPR64u64_GPR64u64 | CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPOXADD_MEMu32_GPR32u32_GPR32u32 | CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPOXADD_MEMu64_GPR64u64_GPR64u64 | CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPPD_XMMpd_MEMpd_IMMb | CMPPD_XMMpd_XMMpd_IMMb | CMPPS_XMMps_MEMps_IMMb | CMPPS_XMMps_XMMps_IMMb | CMPPXADD_MEMu32_GPR32u32_GPR32u32 | CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPPXADD_MEMu64_GPR64u64_GPR64u64 | CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPSB | CMPSD | CMPSD_XMM_XMMsd_MEMsd_IMMb | CMPSD_XMM_XMMsd_XMMsd_IMMb | CMPSQ | CMPSS_XMMss_MEMss_IMMb | CMPSS_XMMss_XMMss_IMMb | CMPSW | CMPSXADD_MEMu32_GPR32u32_GPR32u32 | CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPSXADD_MEMu64_GPR64u64_GPR64u64 | CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX | CMPXCHG_GPR8_GPR8 | CMPXCHG_GPRv_GPRv | CMPXCHG_MEMb_GPR8 | CMPXCHG_MEMv_GPRv | CMPXCHG16B_MEMdq | CMPXCHG16B_LOCK_MEMdq | CMPXCHG8B_MEMq | CMPXCHG8B_LOCK_MEMq | CMPXCHG_LOCK_MEMb_GPR8 | CMPXCHG_LOCK_MEMv_GPRv | CMPZXADD_MEMu32_GPR32u32_GPR32u32 | CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX | CMPZXADD_MEMu64_GPR64u64_GPR64u64 | CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX | COMISD_XMMsd_MEMsd | COMISD_XMMsd_XMMsd | COMISS_XMMss_MEMss | COMISS_XMMss_XMMss | CPUID | CQO | CRC32_GPRy_GPR8i8_APX | CRC32_GPRy_GPRv_APX | CRC32_GPRy_MEMi8_APX | CRC32_GPRy_MEMv_APX | CRC32_GPRyy_GPR8b | CRC32_GPRyy_GPRv | CRC32_GPRyy_MEMb | CRC32_GPRyy_MEMv | CTESTB_GPR8i8_GPR8i8_DFV_APX | CTESTB_GPR8i8_IMM8_DFV_APX | CTESTB_GPRv_GPRv_DFV_APX | CTESTB_GPRv_IMMz_DFV_APX | CTESTB_MEMi8_GPR8i8_DFV_APX | CTESTB_MEMi8_IMM8_DFV_APX | CTESTB_MEMv_GPRv_DFV_APX | CTESTB_MEMv_IMMz_DFV_APX | CTESTBE_GPR8i8_GPR8i8_DFV_APX | CTESTBE_GPR8i8_IMM8_DFV_APX | CTESTBE_GPRv_GPRv_DFV_APX | CTESTBE_GPRv_IMMz_DFV_APX | CTESTBE_MEMi8_GPR8i8_DFV_APX | CTESTBE_MEMi8_IMM8_DFV_APX | CTESTBE_MEMv_GPRv_DFV_APX | CTESTBE_MEMv_IMMz_DFV_APX | CTESTF_GPR8i8_GPR8i8_DFV_APX | CTESTF_GPR8i8_IMM8_DFV_APX | CTESTF_GPRv_GPRv_DFV_APX | CTESTF_GPRv_IMMz_DFV_APX | CTESTF_MEMi8_GPR8i8_DFV_APX | CTESTF_MEMi8_IMM8_DFV_APX | CTESTF_MEMv_GPRv_DFV_APX | CTESTF_MEMv_IMMz_DFV_APX | CTESTL_GPR8i8_GPR8i8_DFV_APX | CTESTL_GPR8i8_IMM8_DFV_APX | CTESTL_GPRv_GPRv_DFV_APX | CTESTL_GPRv_IMMz_DFV_APX | CTESTL_MEMi8_GPR8i8_DFV_APX | CTESTL_MEMi8_IMM8_DFV_APX | CTESTL_MEMv_GPRv_DFV_APX | CTESTL_MEMv_IMMz_DFV_APX | CTESTLE_GPR8i8_GPR8i8_DFV_APX | CTESTLE_GPR8i8_IMM8_DFV_APX | CTESTLE_GPRv_GPRv_DFV_APX | CTESTLE_GPRv_IMMz_DFV_APX | CTESTLE_MEMi8_GPR8i8_DFV_APX | CTESTLE_MEMi8_IMM8_DFV_APX | CTESTLE_MEMv_GPRv_DFV_APX | CTESTLE_MEMv_IMMz_DFV_APX | CTESTNB_GPR8i8_GPR8i8_DFV_APX | CTESTNB_GPR8i8_IMM8_DFV_APX | CTESTNB_GPRv_GPRv_DFV_APX | CTESTNB_GPRv_IMMz_DFV_APX | CTESTNB_MEMi8_GPR8i8_DFV_APX | CTESTNB_MEMi8_IMM8_DFV_APX | CTESTNB_MEMv_GPRv_DFV_APX | CTESTNB_MEMv_IMMz_DFV_APX | CTESTNBE_GPR8i8_GPR8i8_DFV_APX | CTESTNBE_GPR8i8_IMM8_DFV_APX | CTESTNBE_GPRv_GPRv_DFV_APX | CTESTNBE_GPRv_IMMz_DFV_APX | CTESTNBE_MEMi8_GPR8i8_DFV_APX | CTESTNBE_MEMi8_IMM8_DFV_APX | CTESTNBE_MEMv_GPRv_DFV_APX | CTESTNBE_MEMv_IMMz_DFV_APX | CTESTNL_GPR8i8_GPR8i8_DFV_APX | CTESTNL_GPR8i8_IMM8_DFV_APX | CTESTNL_GPRv_GPRv_DFV_APX | CTESTNL_GPRv_IMMz_DFV_APX | CTESTNL_MEMi8_GPR8i8_DFV_APX | CTESTNL_MEMi8_IMM8_DFV_APX | CTESTNL_MEMv_GPRv_DFV_APX | CTESTNL_MEMv_IMMz_DFV_APX | CTESTNLE_GPR8i8_GPR8i8_DFV_APX | CTESTNLE_GPR8i8_IMM8_DFV_APX | CTESTNLE_GPRv_GPRv_DFV_APX | CTESTNLE_GPRv_IMMz_DFV_APX | CTESTNLE_MEMi8_GPR8i8_DFV_APX | CTESTNLE_MEMi8_IMM8_DFV_APX | CTESTNLE_MEMv_GPRv_DFV_APX | CTESTNLE_MEMv_IMMz_DFV_APX | CTESTNO_GPR8i8_GPR8i8_DFV_APX | CTESTNO_GPR8i8_IMM8_DFV_APX | CTESTNO_GPRv_GPRv_DFV_APX | CTESTNO_GPRv_IMMz_DFV_APX | CTESTNO_MEMi8_GPR8i8_DFV_APX | CTESTNO_MEMi8_IMM8_DFV_APX | CTESTNO_MEMv_GPRv_DFV_APX | CTESTNO_MEMv_IMMz_DFV_APX | CTESTNS_GPR8i8_GPR8i8_DFV_APX | CTESTNS_GPR8i8_IMM8_DFV_APX | CTESTNS_GPRv_GPRv_DFV_APX | CTESTNS_GPRv_IMMz_DFV_APX | CTESTNS_MEMi8_GPR8i8_DFV_APX | CTESTNS_MEMi8_IMM8_DFV_APX | CTESTNS_MEMv_GPRv_DFV_APX | CTESTNS_MEMv_IMMz_DFV_APX | CTESTNZ_GPR8i8_GPR8i8_DFV_APX | CTESTNZ_GPR8i8_IMM8_DFV_APX | CTESTNZ_GPRv_GPRv_DFV_APX | CTESTNZ_GPRv_IMMz_DFV_APX | CTESTNZ_MEMi8_GPR8i8_DFV_APX | CTESTNZ_MEMi8_IMM8_DFV_APX | CTESTNZ_MEMv_GPRv_DFV_APX | CTESTNZ_MEMv_IMMz_DFV_APX | CTESTO_GPR8i8_GPR8i8_DFV_APX | CTESTO_GPR8i8_IMM8_DFV_APX | CTESTO_GPRv_GPRv_DFV_APX | CTESTO_GPRv_IMMz_DFV_APX | CTESTO_MEMi8_GPR8i8_DFV_APX | CTESTO_MEMi8_IMM8_DFV_APX | CTESTO_MEMv_GPRv_DFV_APX | CTESTO_MEMv_IMMz_DFV_APX | CTESTS_GPR8i8_GPR8i8_DFV_APX | CTESTS_GPR8i8_IMM8_DFV_APX | CTESTS_GPRv_GPRv_DFV_APX | CTESTS_GPRv_IMMz_DFV_APX | CTESTS_MEMi8_GPR8i8_DFV_APX | CTESTS_MEMi8_IMM8_DFV_APX | CTESTS_MEMv_GPRv_DFV_APX | CTESTS_MEMv_IMMz_DFV_APX | CTESTT_GPR8i8_GPR8i8_DFV_APX | CTESTT_GPR8i8_IMM8_DFV_APX | CTESTT_GPRv_GPRv_DFV_APX | CTESTT_GPRv_IMMz_DFV_APX | CTESTT_MEMi8_GPR8i8_DFV_APX | CTESTT_MEMi8_IMM8_DFV_APX | CTESTT_MEMv_GPRv_DFV_APX | CTESTT_MEMv_IMMz_DFV_APX | CTESTZ_GPR8i8_GPR8i8_DFV_APX | CTESTZ_GPR8i8_IMM8_DFV_APX | CTESTZ_GPRv_GPRv_DFV_APX | CTESTZ_GPRv_IMMz_DFV_APX | CTESTZ_MEMi8_GPR8i8_DFV_APX | CTESTZ_MEMi8_IMM8_DFV_APX | CTESTZ_MEMv_GPRv_DFV_APX | CTESTZ_MEMv_IMMz_DFV_APX | CVTDQ2PD_XMMpd_MEMq | CVTDQ2PD_XMMpd_XMMq | CVTDQ2PS_XMMps_MEMdq | CVTDQ2PS_XMMps_XMMdq | CVTPD2DQ_XMMdq_MEMpd | CVTPD2DQ_XMMdq_XMMpd | CVTPD2PI_MMXq_MEMpd | CVTPD2PI_MMXq_XMMpd | CVTPD2PS_XMMps_MEMpd | CVTPD2PS_XMMps_XMMpd | CVTPI2PD_XMMpd_MEMq | CVTPI2PD_XMMpd_MMXq | CVTPI2PS_XMMq_MEMq | CVTPI2PS_XMMq_MMXq | CVTPS2DQ_XMMdq_MEMps | CVTPS2DQ_XMMdq_XMMps | CVTPS2PD_XMMpd_MEMq | CVTPS2PD_XMMpd_XMMq | CVTPS2PI_MMXq_MEMq | CVTPS2PI_MMXq_XMMq | CVTSD2SI_GPR32d_MEMsd | CVTSD2SI_GPR32d_XMMsd | CVTSD2SI_GPR64q_MEMsd | CVTSD2SI_GPR64q_XMMsd | CVTSD2SS_XMMss_MEMsd | CVTSD2SS_XMMss_XMMsd | CVTSI2SD_XMMsd_GPR32d | CVTSI2SD_XMMsd_GPR64q | CVTSI2SD_XMMsd_MEMd | CVTSI2SD_XMMsd_MEMq | CVTSI2SS_XMMss_GPR32d | CVTSI2SS_XMMss_GPR64q | CVTSI2SS_XMMss_MEMd | CVTSI2SS_XMMss_MEMq | CVTSS2SD_XMMsd_MEMss | CVTSS2SD_XMMsd_XMMss | CVTSS2SI_GPR32d_MEMss | CVTSS2SI_GPR32d_XMMss | CVTSS2SI_GPR64q_MEMss | CVTSS2SI_GPR64q_XMMss | CVTTPD2DQ_XMMdq_MEMpd | CVTTPD2DQ_XMMdq_XMMpd | CVTTPD2PI_MMXq_MEMpd | CVTTPD2PI_MMXq_XMMpd | CVTTPS2DQ_XMMdq_MEMps | CVTTPS2DQ_XMMdq_XMMps | CVTTPS2PI_MMXq_MEMq | CVTTPS2PI_MMXq_XMMq | CVTTSD2SI_GPR32d_MEMsd | CVTTSD2SI_GPR32d_XMMsd | CVTTSD2SI_GPR64q_MEMsd | CVTTSD2SI_GPR64q_XMMsd | CVTTSS2SI_GPR32d_MEMss | CVTTSS2SI_GPR32d_XMMss | CVTTSS2SI_GPR64q_MEMss | CVTTSS2SI_GPR64q_XMMss | CWD | CWDE | DAA | DAS | DEC_GPR8 | DEC_GPR8i8_APX | DEC_GPR8i8_GPR8i8_APX | DEC_GPR8i8_MEMi8_APX | DEC_GPRv_48 | DEC_GPRv_APX | DEC_GPRv_FFr1 | DEC_GPRv_GPRv_APX | DEC_GPRv_MEMv_APX | DEC_MEMb | DEC_MEMi8_APX | DEC_MEMv | DEC_MEMv_APX | DEC_LOCK_MEMb | DEC_LOCK_MEMv | DIV_GPR8 | DIV_GPR8i8_APX | DIV_GPRv | DIV_GPRv_APX | DIV_MEMb | DIV_MEMi8_APX | DIV_MEMv | DIV_MEMv_APX | DIVPD_XMMpd_MEMpd | DIVPD_XMMpd_XMMpd | DIVPS_XMMps_MEMps | DIVPS_XMMps_XMMps | DIVSD_XMMsd_MEMsd | DIVSD_XMMsd_XMMsd | DIVSS_XMMss_MEMss | DIVSS_XMMss_XMMss | DPPD_XMMdq_MEMdq_IMMb | DPPD_XMMdq_XMMdq_IMMb | DPPS_XMMdq_MEMdq_IMMb | DPPS_XMMdq_XMMdq_IMMb | EMMS | ENCLS | ENCLU | ENCLV | ENCODEKEY128_GPR32u8_GPR32u8 | ENCODEKEY256_GPR32u8_GPR32u8 | ENDBR32 | ENDBR64 | ENQCMD_GPRa_MEMu32 | ENQCMD_GPRav_MEMu32_APX | ENQCMDS_GPRa_MEMu32 | ENQCMDS_GPRav_MEMu32_APX | ENTER_IMMw_IMMb | ERETS | ERETU | EXTRACTPS_GPR32d_XMMdq_IMMb | EXTRACTPS_MEMd_XMMps_IMMb | EXTRQ_XMMq_IMMb_IMMb | EXTRQ_XMMq_XMMdq | F2XM1 | FABS | FADD_MEMm64real | FADD_MEMmem32real | FADD_ST0_X87 | FADD_X87_ST0 | FADDP_X87_ST0 | FBLD_ST0_MEMmem80dec | FBSTP_MEMmem80dec_ST0 | FCHS | FCMOVB_ST0_X87 | FCMOVBE_ST0_X87 | FCMOVE_ST0_X87 | FCMOVNB_ST0_X87 | FCMOVNBE_ST0_X87 | FCMOVNE_ST0_X87 | FCMOVNU_ST0_X87 | FCMOVU_ST0_X87 | FCOM_ST0_MEMm64real | FCOM_ST0_MEMmem32real | FCOM_ST0_X87 | FCOM_ST0_X87_DCD0 | FCOMI_ST0_X87 | FCOMIP_ST0_X87 | FCOMP_ST0_MEMm64real | FCOMP_ST0_MEMmem32real | FCOMP_ST0_X87 | FCOMP_ST0_X87_DCD1 | FCOMP_ST0_X87_DED0 | FCOMPP | FCOS | FDECSTP | FDISI8087_NOP | FDIV_ST0_MEMm64real | FDIV_ST0_MEMmem32real | FDIV_ST0_X87 | FDIV_X87_ST0 | FDIVP_X87_ST0 | FDIVR_ST0_MEMm64real | FDIVR_ST0_MEMmem32real | FDIVR_ST0_X87 | FDIVR_X87_ST0 | FDIVRP_X87_ST0 | FEMMS | FENI8087_NOP | FFREE_X87 | FFREEP_X87 | FIADD_ST0_MEMmem16int | FIADD_ST0_MEMmem32int | FICOM_ST0_MEMmem16int | FICOM_ST0_MEMmem32int | FICOMP_ST0_MEMmem16int | FICOMP_ST0_MEMmem32int | FIDIV_ST0_MEMmem16int | FIDIV_ST0_MEMmem32int | FIDIVR_ST0_MEMmem16int | FIDIVR_ST0_MEMmem32int | FILD_ST0_MEMm64int | FILD_ST0_MEMmem16int | FILD_ST0_MEMmem32int | FIMUL_ST0_MEMmem16int | FIMUL_ST0_MEMmem32int | FINCSTP | FIST_MEMmem16int_ST0 | FIST_MEMmem32int_ST0 | FISTP_MEMm64int_ST0 | FISTP_MEMmem16int_ST0 | FISTP_MEMmem32int_ST0 | FISTTP_MEMm64int_ST0 | FISTTP_MEMmem16int_ST0 | FISTTP_MEMmem32int_ST0 | FISUB_ST0_MEMmem16int | FISUB_ST0_MEMmem32int | FISUBR_ST0_MEMmem16int | FISUBR_ST0_MEMmem32int | FLD_ST0_MEMm64real | FLD_ST0_MEMmem32real | FLD_ST0_MEMmem80real | FLD_ST0_X87 | FLD1 | FLDCW_MEMmem16 | FLDENV_MEMmem14 | FLDENV_MEMmem28 | FLDL2E | FLDL2T | FLDLG2 | FLDLN2 | FLDPI | FLDZ | FMUL_ST0_MEMm64real | FMUL_ST0_MEMmem32real | FMUL_ST0_X87 | FMUL_X87_ST0 | FMULP_X87_ST0 | FNCLEX | FNINIT | FNOP | FNSAVE_MEMmem108 | FNSAVE_MEMmem94 | FNSTCW_MEMmem16 | FNSTENV_MEMmem14 | FNSTENV_MEMmem28 | FNSTSW_AX | FNSTSW_MEMmem16 | FPATAN | FPREM | FPREM1 | FPTAN | FRNDINT | FRSTOR_MEMmem108 | FRSTOR_MEMmem94 | FSCALE | FSETPM287_NOP | FSIN | FSINCOS | FSQRT | FST_MEMm64real_ST0 | FST_MEMmem32real_ST0 | FST_X87_ST0 | FSTP_MEMm64real_ST0 | FSTP_MEMmem32real_ST0 | FSTP_MEMmem80real_ST0 | FSTP_X87_ST0 | FSTP_X87_ST0_DFD0 | FSTP_X87_ST0_DFD1 | FSTPNCE_X87_ST0 | FSUB_ST0_MEMm64real | FSUB_ST0_MEMmem32real | FSUB_ST0_X87 | FSUB_X87_ST0 | FSUBP_X87_ST0 | FSUBR_ST0_MEMm64real | FSUBR_ST0_MEMmem32real | FSUBR_ST0_X87 | FSUBR_X87_ST0 | FSUBRP_X87_ST0 | FTST | FUCOM_ST0_X87 | FUCOMI_ST0_X87 | FUCOMIP_ST0_X87 | FUCOMP_ST0_X87 | FUCOMPP | FWAIT | FXAM | FXCH_ST0_X87 | FXCH_ST0_X87_DDC1 | FXCH_ST0_X87_DFC1 | FXRSTOR_MEMmfpxenv | FXRSTOR64_MEMmfpxenv | FXSAVE_MEMmfpxenv | FXSAVE64_MEMmfpxenv | FXTRACT | FYL2X | FYL2XP1 | GETSEC | GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 | GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 | GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 | GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 | GF2P8MULB_XMMu8_MEMu8 | GF2P8MULB_XMMu8_XMMu8 | HADDPD_XMMpd_MEMpd | HADDPD_XMMpd_XMMpd | HADDPS_XMMps_MEMps | HADDPS_XMMps_XMMps | HLT | HRESET_IMM8 | HSUBPD_XMMpd_MEMpd | HSUBPD_XMMpd_XMMpd | HSUBPS_XMMps_MEMps | HSUBPS_XMMps_XMMps | IDIV_GPR8 | IDIV_GPR8i8_APX | IDIV_GPRv | IDIV_GPRv_APX | IDIV_MEMb | IDIV_MEMi8_APX | IDIV_MEMv | IDIV_MEMv_APX | IMUL_GPR8 | IMUL_GPR8i8_APX | IMUL_GPRv | IMUL_GPRv_APX | IMUL_GPRv_GPRv | IMUL_GPRv_GPRv_APX | IMUL_GPRv_GPRv_GPRv_APX | IMUL_GPRv_GPRv_IMM8_APX | IMUL_GPRv_GPRv_IMM8_APX_ZU | IMUL_GPRv_GPRv_IMMb | IMUL_GPRv_GPRv_IMMz | IMUL_GPRv_GPRv_IMMz_APX | IMUL_GPRv_GPRv_IMMz_APX_ZU | IMUL_GPRv_GPRv_MEMv_APX | IMUL_GPRv_MEMv | IMUL_GPRv_MEMv_APX | IMUL_GPRv_MEMv_IMM8_APX | IMUL_GPRv_MEMv_IMM8_APX_ZU | IMUL_GPRv_MEMv_IMMb | IMUL_GPRv_MEMv_IMMz | IMUL_GPRv_MEMv_IMMz_APX | IMUL_GPRv_MEMv_IMMz_APX_ZU | IMUL_MEMb | IMUL_MEMi8_APX | IMUL_MEMv | IMUL_MEMv_APX | IN_AL_DX | IN_AL_IMMb | IN_OeAX_DX | IN_OeAX_IMMb | INC_GPR8 | INC_GPR8i8_APX | INC_GPR8i8_GPR8i8_APX | INC_GPR8i8_MEMi8_APX | INC_GPRv_40 | INC_GPRv_APX | INC_GPRv_FFr0 | INC_GPRv_GPRv_APX | INC_GPRv_MEMv_APX | INC_MEMb | INC_MEMi8_APX | INC_MEMv | INC_MEMv_APX | INCSSPD_GPR32u8 | INCSSPQ_GPR64u8 | INC_LOCK_MEMb | INC_LOCK_MEMv | INSB | INSD | INSERTPS_XMMps_MEMd_IMMb | INSERTPS_XMMps_XMMps_IMMb | INSERTQ_XMMq_XMMdq | INSERTQ_XMMq_XMMq_IMMb_IMMb | INSW | INT_IMMb | INT1 | INT3 | INTO | INVD | INVEPT_GPR32_MEMdq | INVEPT_GPR64_MEMdq | INVEPT_GPR64i64_MEMi128_APX | INVLPG_MEMb | INVLPGA_ArAX_ECX | INVLPGB_EAX_EDX_ECX | INVLPGB_RAX_EDX_ECX | INVPCID_GPR32_MEMdq | INVPCID_GPR64_MEMdq | INVPCID_GPR64i64_MEMi128_APX | INVVPID_GPR32_MEMdq | INVVPID_GPR64_MEMdq | INVVPID_GPR64i64_MEMi128_APX | IRET | IRETD | IRETQ | JB_RELBRb | JB_RELBRd | JB_RELBRz | JBE_RELBRb | JBE_RELBRd | JBE_RELBRz | JCXZ_RELBRb | JECXZ_RELBRb | JL_RELBRb | JL_RELBRd | JL_RELBRz | JLE_RELBRb | JLE_RELBRd | JLE_RELBRz | JMP_GPRv | JMP_MEMv | JMP_RELBRb | JMP_RELBRd | JMP_RELBRz | JMPABS_ABSBRu64_APX | JMP_FAR_MEMp2 | JMP_FAR_PTRp_IMMw | JNB_RELBRb | JNB_RELBRd | JNB_RELBRz | JNBE_RELBRb | JNBE_RELBRd | JNBE_RELBRz | JNL_RELBRb | JNL_RELBRd | JNL_RELBRz | JNLE_RELBRb | JNLE_RELBRd | JNLE_RELBRz | JNO_RELBRb | JNO_RELBRd | JNO_RELBRz | JNP_RELBRb | JNP_RELBRd | JNP_RELBRz | JNS_RELBRb | JNS_RELBRd | JNS_RELBRz | JNZ_RELBRb | JNZ_RELBRd | JNZ_RELBRz | JO_RELBRb | JO_RELBRd | JO_RELBRz | JP_RELBRb | JP_RELBRd | JP_RELBRz | JRCXZ_RELBRb | JS_RELBRb | JS_RELBRd | JS_RELBRz | JZ_RELBRb | JZ_RELBRd | JZ_RELBRz | KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 | KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 | KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 | KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 | KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 | KMOVB_GPR32u32_MASKmskw_APX | KMOVB_GPR32u32_MASKmskw_AVX512 | KMOVB_MASKmskw_GPR32u32_APX | KMOVB_MASKmskw_GPR32u32_AVX512 | KMOVB_MASKmskw_MASKu8_APX | KMOVB_MASKmskw_MASKu8_AVX512 | KMOVB_MASKmskw_MEMu8_APX | KMOVB_MASKmskw_MEMu8_AVX512 | KMOVB_MEMu8_MASKmskw_APX | KMOVB_MEMu8_MASKmskw_AVX512 | KMOVD_GPR32u32_MASKmskw_APX | KMOVD_GPR32u32_MASKmskw_AVX512 | KMOVD_MASKmskw_GPR32u32_APX | KMOVD_MASKmskw_GPR32u32_AVX512 | KMOVD_MASKmskw_MASKu32_APX | KMOVD_MASKmskw_MASKu32_AVX512 | KMOVD_MASKmskw_MEMu32_APX | KMOVD_MASKmskw_MEMu32_AVX512 | KMOVD_MEMu32_MASKmskw_APX | KMOVD_MEMu32_MASKmskw_AVX512 | KMOVQ_GPR64u64_MASKmskw_APX | KMOVQ_GPR64u64_MASKmskw_AVX512 | KMOVQ_MASKmskw_GPR64u64_APX | KMOVQ_MASKmskw_GPR64u64_AVX512 | KMOVQ_MASKmskw_MASKu64_APX | KMOVQ_MASKmskw_MASKu64_AVX512 | KMOVQ_MASKmskw_MEMu64_APX | KMOVQ_MASKmskw_MEMu64_AVX512 | KMOVQ_MEMu64_MASKmskw_APX | KMOVQ_MEMu64_MASKmskw_AVX512 | KMOVW_GPR32u32_MASKmskw_APX | KMOVW_GPR32u32_MASKmskw_AVX512 | KMOVW_MASKmskw_GPR32u32_APX | KMOVW_MASKmskw_GPR32u32_AVX512 | KMOVW_MASKmskw_MASKu16_APX | KMOVW_MASKmskw_MASKu16_AVX512 | KMOVW_MASKmskw_MEMu16_APX | KMOVW_MASKmskw_MEMu16_AVX512 | KMOVW_MEMu16_MASKmskw_APX | KMOVW_MEMu16_MASKmskw_AVX512 | KNOTB_MASKmskw_MASKmskw_AVX512 | KNOTD_MASKmskw_MASKmskw_AVX512 | KNOTQ_MASKmskw_MASKmskw_AVX512 | KNOTW_MASKmskw_MASKmskw_AVX512 | KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 | KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 | KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 | KORTESTB_MASKmskw_MASKmskw_AVX512 | KORTESTD_MASKmskw_MASKmskw_AVX512 | KORTESTQ_MASKmskw_MASKmskw_AVX512 | KORTESTW_MASKmskw_MASKmskw_AVX512 | KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 | KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 | KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 | KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 | KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 | KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 | KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 | KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 | KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 | KTESTB_MASKmskw_MASKmskw_AVX512 | KTESTD_MASKmskw_MASKmskw_AVX512 | KTESTQ_MASKmskw_MASKmskw_AVX512 | KTESTW_MASKmskw_MASKmskw_AVX512 | KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 | KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 | KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 | KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 | LAHF | LAR_GPRv_GPRv | LAR_GPRv_MEMw | LDDQU_XMMpd_MEMdq | LDMXCSR_MEMd | LDS_GPRz_MEMp | LDTILECFG_MEM | LDTILECFG_MEM_APX | LEA_GPRv_AGEN | LEAVE | LES_GPRz_MEMp | LFENCE | LFS_GPRv_MEMp2 | LGDT_MEMs | LGDT_MEMs64 | LGS_GPRv_MEMp2 | LIDT_MEMs | LIDT_MEMs64 | LKGS_GPR16u16 | LKGS_MEMu16 | LLDT_GPR16 | LLDT_MEMw | LLWPCB_GPRyy | LMSW_GPR16 | LMSW_MEMw | LOADIWKEY_XMMu8_XMMu8 | LODSB | LODSD | LODSQ | LODSW | LOOP_RELBRb | LOOPE_RELBRb | LOOPNE_RELBRb | LSL_GPRv_GPRz | LSL_GPRv_MEMw | LSS_GPRv_MEMp2 | LTR_GPR16 | LTR_MEMw | LWPINS_GPRyy_GPR32d_IMMd | LWPINS_GPRyy_MEMd_IMMd | LWPVAL_GPRyy_GPR32d_IMMd | LWPVAL_GPRyy_MEMd_IMMd | LZCNT_GPRv_GPRv | LZCNT_GPRv_GPRv_APX | LZCNT_GPRv_MEMv | LZCNT_GPRv_MEMv_APX | MASKMOVDQU_XMMxub_XMMxub | MASKMOVQ_MMXq_MMXq | MAXPD_XMMpd_MEMpd | MAXPD_XMMpd_XMMpd | MAXPS_XMMps_MEMps | MAXPS_XMMps_XMMps | MAXSD_XMMsd_MEMsd | MAXSD_XMMsd_XMMsd | MAXSS_XMMss_MEMss | MAXSS_XMMss_XMMss | MCOMMIT | MFENCE | MINPD_XMMpd_MEMpd | MINPD_XMMpd_XMMpd | MINPS_XMMps_MEMps | MINPS_XMMps_XMMps | MINSD_XMMsd_MEMsd | MINSD_XMMsd_XMMsd | MINSS_XMMss_MEMss | MINSS_XMMss_XMMss | MONITOR | MONITORX | MOV_AL_MEMb | MOV_GPR8_GPR8_88 | MOV_GPR8_GPR8_8A | MOV_GPR8_IMMb_B0 | MOV_GPR8_IMMb_C6r0 | MOV_GPR8_MEMb | MOV_GPRv_GPRv_89 | MOV_GPRv_GPRv_8B | MOV_GPRv_IMMv | MOV_GPRv_IMMz | MOV_GPRv_MEMv | MOV_GPRv_SEG | MOV_MEMb_AL | MOV_MEMb_GPR8 | MOV_MEMb_IMMb | MOV_MEMv_GPRv | MOV_MEMv_IMMz | MOV_MEMv_OrAX | MOV_MEMw_SEG | MOV_OrAX_MEMv | MOV_SEG_GPR16 | MOV_SEG_MEMw | MOVAPD_MEMpd_XMMpd | MOVAPD_XMMpd_MEMpd | MOVAPD_XMMpd_XMMpd_0F28 | MOVAPD_XMMpd_XMMpd_0F29 | MOVAPS_MEMps_XMMps | MOVAPS_XMMps_MEMps | MOVAPS_XMMps_XMMps_0F28 | MOVAPS_XMMps_XMMps_0F29 | MOVBE_GPRv_GPRv_APX | MOVBE_GPRv_MEMv | MOVBE_GPRv_MEMv_APX | MOVBE_MEMv_GPRv | MOVBE_MEMv_GPRv_APX | MOVD_GPR32_MMXd | MOVD_GPR32_XMMd | MOVD_MEMd_MMXd | MOVD_MEMd_XMMd | MOVD_MMXq_GPR32 | MOVD_MMXq_MEMd | MOVD_XMMdq_GPR32 | MOVD_XMMdq_MEMd | MOVDDUP_XMMdq_MEMq | MOVDDUP_XMMdq_XMMq | MOVDIR64B_GPRa_MEM | MOVDIR64B_GPRav_MEMu32_APX | MOVDIRI_MEMu32_GPR32u32 | MOVDIRI_MEMu64_GPR64u64 | MOVDIRI_MEMyu_GPRyu_APX | MOVDQ2Q_MMXq_XMMq | MOVDQA_MEMdq_XMMdq | MOVDQA_XMMdq_MEMdq | MOVDQA_XMMdq_XMMdq_0F6F | MOVDQA_XMMdq_XMMdq_0F7F | MOVDQU_MEMdq_XMMdq | MOVDQU_XMMdq_MEMdq | MOVDQU_XMMdq_XMMdq_0F6F | MOVDQU_XMMdq_XMMdq_0F7F | MOVHLPS_XMMq_XMMq | MOVHPD_MEMq_XMMsd | MOVHPD_XMMsd_MEMq | MOVHPS_MEMq_XMMps | MOVHPS_XMMq_MEMq | MOVLHPS_XMMq_XMMq | MOVLPD_MEMq_XMMsd | MOVLPD_XMMsd_MEMq | MOVLPS_MEMq_XMMq | MOVLPS_XMMq_MEMq | MOVMSKPD_GPR32_XMMpd | MOVMSKPS_GPR32_XMMps | MOVNTDQ_MEMdq_XMMdq | MOVNTDQA_XMMdq_MEMdq | MOVNTI_MEMd_GPR32 | MOVNTI_MEMq_GPR64 | MOVNTPD_MEMdq_XMMpd | MOVNTPS_MEMdq_XMMps | MOVNTQ_MEMq_MMXq | MOVNTSD_MEMq_XMMq | MOVNTSS_MEMd_XMMd | MOVQ_GPR64_MMXq | MOVQ_GPR64_XMMq | MOVQ_MEMq_MMXq_0F7E | MOVQ_MEMq_MMXq_0F7F | MOVQ_MEMq_XMMq_0F7E | MOVQ_MEMq_XMMq_0FD6 | MOVQ_MMXq_GPR64 | MOVQ_MMXq_MEMq_0F6E | MOVQ_MMXq_MEMq_0F6F | MOVQ_MMXq_MMXq_0F6F | MOVQ_MMXq_MMXq_0F7F | MOVQ_XMMdq_GPR64 | MOVQ_XMMdq_MEMq_0F6E | MOVQ_XMMdq_MEMq_0F7E | MOVQ_XMMdq_XMMq_0F7E | MOVQ_XMMdq_XMMq_0FD6 | MOVQ2DQ_XMMdq_MMXq | MOVSB | MOVSD | MOVSD_XMM_MEMsd_XMMsd | MOVSD_XMM_XMMdq_MEMsd | MOVSD_XMM_XMMsd_XMMsd_0F10 | MOVSD_XMM_XMMsd_XMMsd_0F11 | MOVSHDUP_XMMps_MEMps | MOVSHDUP_XMMps_XMMps | MOVSLDUP_XMMps_MEMps | MOVSLDUP_XMMps_XMMps | MOVSQ | MOVSS_MEMss_XMMss | MOVSS_XMMdq_MEMss | MOVSS_XMMss_XMMss_0F10 | MOVSS_XMMss_XMMss_0F11 | MOVSW | MOVSX_GPRv_GPR16 | MOVSX_GPRv_GPR8 | MOVSX_GPRv_MEMb | MOVSX_GPRv_MEMw | MOVSXD_GPRv_GPRz | MOVSXD_GPRv_MEMz | MOVUPD_MEMpd_XMMpd | MOVUPD_XMMpd_MEMpd | MOVUPD_XMMpd_XMMpd_0F10 | MOVUPD_XMMpd_XMMpd_0F11 | MOVUPS_MEMps_XMMps | MOVUPS_XMMps_MEMps | MOVUPS_XMMps_XMMps_0F10 | MOVUPS_XMMps_XMMps_0F11 | MOVZX_GPRv_GPR16 | MOVZX_GPRv_GPR8 | MOVZX_GPRv_MEMb | MOVZX_GPRv_MEMw | MOV_CR_CR_GPR32 | MOV_CR_CR_GPR64 | MOV_CR_GPR32_CR | MOV_CR_GPR64_CR | MOV_DR_DR_GPR32 | MOV_DR_DR_GPR64 | MOV_DR_GPR32_DR | MOV_DR_GPR64_DR | MPSADBW_XMMdq_MEMdq_IMMb | MPSADBW_XMMdq_XMMdq_IMMb | MUL_GPR8 | MUL_GPR8i8_APX | MUL_GPRv | MUL_GPRv_APX | MUL_MEMb | MUL_MEMi8_APX | MUL_MEMv | MUL_MEMv_APX | MULPD_XMMpd_MEMpd | MULPD_XMMpd_XMMpd | MULPS_XMMps_MEMps | MULPS_XMMps_XMMps | MULSD_XMMsd_MEMsd | MULSD_XMMsd_XMMsd | MULSS_XMMss_MEMss | MULSS_XMMss_XMMss | MULX_GPR32d_GPR32d_GPR32d | MULX_GPR32d_GPR32d_MEMd | MULX_GPR32i32_GPR32i32_GPR32i32_APX | MULX_GPR32i32_GPR32i32_MEMi32_APX | MULX_GPR64i64_GPR64i64_GPR64i64_APX | MULX_GPR64i64_GPR64i64_MEMi64_APX | MULX_GPR64q_GPR64q_GPR64q | MULX_GPR64q_GPR64q_MEMq | MWAIT | MWAITX | NEG_GPR8 | NEG_GPR8i8_APX | NEG_GPR8i8_GPR8i8_APX | NEG_GPR8i8_MEMi8_APX | NEG_GPRv | NEG_GPRv_APX | NEG_GPRv_GPRv_APX | NEG_GPRv_MEMv_APX | NEG_MEMb | NEG_MEMi8_APX | NEG_MEMv | NEG_MEMv_APX | NEG_LOCK_MEMb | NEG_LOCK_MEMv | NOP_90 | NOP_GPRv_0F18r0 | NOP_GPRv_0F18r1 | NOP_GPRv_0F18r2 | NOP_GPRv_0F18r3 | NOP_GPRv_0F18r4 | NOP_GPRv_0F18r5 | NOP_GPRv_0F18r6 | NOP_GPRv_0F18r7 | NOP_GPRv_0F1F | NOP_GPRv_GPRv_0F0D | NOP_GPRv_GPRv_0F19 | NOP_GPRv_GPRv_0F1A | NOP_GPRv_GPRv_0F1B | NOP_GPRv_GPRv_0F1C | NOP_GPRv_GPRv_0F1D | NOP_GPRv_GPRv_0F1E | NOP_GPRv_MEM_0F1B | NOP_GPRv_MEMv_0F1A | NOP_MEMv_0F18r4 | NOP_MEMv_0F18r5 | NOP_MEMv_0F1F | NOP_MEMv_GPRv_0F19 | NOP_MEMv_GPRv_0F1C | NOP_MEMv_GPRv_0F1D | NOP_MEMv_GPRv_0F1E | NOT_GPR8 | NOT_GPR8i8_APX | NOT_GPR8i8_GPR8i8_APX | NOT_GPR8i8_MEMi8_APX | NOT_GPRv | NOT_GPRv_APX | NOT_GPRv_GPRv_APX | NOT_GPRv_MEMv_APX | NOT_MEMb | NOT_MEMi8_APX | NOT_MEMv | NOT_MEMv_APX | NOT_LOCK_MEMb | NOT_LOCK_MEMv | OR_AL_IMMb | OR_GPR8_GPR8_08 | OR_GPR8_GPR8_0A | OR_GPR8_IMMb_80r1 | OR_GPR8_IMMb_82r1 | OR_GPR8_MEMb | OR_GPR8i8_GPR8i8_APX | OR_GPR8i8_GPR8i8_GPR8i8_APX | OR_GPR8i8_GPR8i8_IMM8_APX | OR_GPR8i8_GPR8i8_MEMi8_APX | OR_GPR8i8_IMM8_APX | OR_GPR8i8_MEMi8_APX | OR_GPR8i8_MEMi8_GPR8i8_APX | OR_GPR8i8_MEMi8_IMM8_APX | OR_GPRv_GPRv_09 | OR_GPRv_GPRv_0B | OR_GPRv_GPRv_APX | OR_GPRv_GPRv_GPRv_APX | OR_GPRv_GPRv_IMM8_APX | OR_GPRv_GPRv_IMMz_APX | OR_GPRv_GPRv_MEMv_APX | OR_GPRv_IMM8_APX | OR_GPRv_IMMb | OR_GPRv_IMMz | OR_GPRv_IMMz_APX | OR_GPRv_MEMv | OR_GPRv_MEMv_APX | OR_GPRv_MEMv_GPRv_APX | OR_GPRv_MEMv_IMM8_APX | OR_GPRv_MEMv_IMMz_APX | OR_MEMb_GPR8 | OR_MEMb_IMMb_80r1 | OR_MEMb_IMMb_82r1 | OR_MEMi8_GPR8i8_APX | OR_MEMi8_IMM8_APX | OR_MEMv_GPRv | OR_MEMv_GPRv_APX | OR_MEMv_IMM8_APX | OR_MEMv_IMMb | OR_MEMv_IMMz | OR_MEMv_IMMz_APX | OR_OrAX_IMMz | ORPD_XMMxuq_MEMxuq | ORPD_XMMxuq_XMMxuq | ORPS_XMMxud_MEMxud | ORPS_XMMxud_XMMxud | OR_LOCK_MEMb_GPR8 | OR_LOCK_MEMb_IMMb_80r1 | OR_LOCK_MEMb_IMMb_82r1 | OR_LOCK_MEMv_GPRv | OR_LOCK_MEMv_IMMb | OR_LOCK_MEMv_IMMz | OUT_DX_AL | OUT_DX_OeAX | OUT_IMMb_AL | OUT_IMMb_OeAX | OUTSB | OUTSD | OUTSW | PABSB_MMXq_MEMq | PABSB_MMXq_MMXq | PABSB_XMMdq_MEMdq | PABSB_XMMdq_XMMdq | PABSD_MMXq_MEMq | PABSD_MMXq_MMXq | PABSD_XMMdq_MEMdq | PABSD_XMMdq_XMMdq | PABSW_MMXq_MEMq | PABSW_MMXq_MMXq | PABSW_XMMdq_MEMdq | PABSW_XMMdq_XMMdq | PACKSSDW_MMXq_MEMq | PACKSSDW_MMXq_MMXq | PACKSSDW_XMMdq_MEMdq | PACKSSDW_XMMdq_XMMdq | PACKSSWB_MMXq_MEMq | PACKSSWB_MMXq_MMXq | PACKSSWB_XMMdq_MEMdq | PACKSSWB_XMMdq_XMMdq | PACKUSDW_XMMdq_MEMdq | PACKUSDW_XMMdq_XMMdq | PACKUSWB_MMXq_MEMq | PACKUSWB_MMXq_MMXq | PACKUSWB_XMMdq_MEMdq | PACKUSWB_XMMdq_XMMdq | PADDB_MMXq_MEMq | PADDB_MMXq_MMXq | PADDB_XMMdq_MEMdq | PADDB_XMMdq_XMMdq | PADDD_MMXq_MEMq | PADDD_MMXq_MMXq | PADDD_XMMdq_MEMdq | PADDD_XMMdq_XMMdq | PADDQ_MMXq_MEMq | PADDQ_MMXq_MMXq | PADDQ_XMMdq_MEMdq | PADDQ_XMMdq_XMMdq | PADDSB_MMXq_MEMq | PADDSB_MMXq_MMXq | PADDSB_XMMdq_MEMdq | PADDSB_XMMdq_XMMdq | PADDSW_MMXq_MEMq | PADDSW_MMXq_MMXq | PADDSW_XMMdq_MEMdq | PADDSW_XMMdq_XMMdq | PADDUSB_MMXq_MEMq | PADDUSB_MMXq_MMXq | PADDUSB_XMMdq_MEMdq | PADDUSB_XMMdq_XMMdq | PADDUSW_MMXq_MEMq | PADDUSW_MMXq_MMXq | PADDUSW_XMMdq_MEMdq | PADDUSW_XMMdq_XMMdq | PADDW_MMXq_MEMq | PADDW_MMXq_MMXq | PADDW_XMMdq_MEMdq | PADDW_XMMdq_XMMdq | PALIGNR_MMXq_MEMq_IMMb | PALIGNR_MMXq_MMXq_IMMb | PALIGNR_XMMdq_MEMdq_IMMb | PALIGNR_XMMdq_XMMdq_IMMb | PAND_MMXq_MEMq | PAND_MMXq_MMXq | PAND_XMMdq_MEMdq | PAND_XMMdq_XMMdq | PANDN_MMXq_MEMq | PANDN_MMXq_MMXq | PANDN_XMMdq_MEMdq | PANDN_XMMdq_XMMdq | PAUSE | PAVGB_MMXq_MEMq | PAVGB_MMXq_MMXq | PAVGB_XMMdq_MEMdq | PAVGB_XMMdq_XMMdq | PAVGUSB_MMXq_MEMq | PAVGUSB_MMXq_MMXq | PAVGW_MMXq_MEMq | PAVGW_MMXq_MMXq | PAVGW_XMMdq_MEMdq | PAVGW_XMMdq_XMMdq | PBLENDVB_XMMdq_MEMdq | PBLENDVB_XMMdq_XMMdq | PBLENDW_XMMdq_MEMdq_IMMb | PBLENDW_XMMdq_XMMdq_IMMb | PBNDKB | PCLMULQDQ_XMMdq_MEMdq_IMMb | PCLMULQDQ_XMMdq_XMMdq_IMMb | PCMPEQB_MMXq_MEMq | PCMPEQB_MMXq_MMXq | PCMPEQB_XMMdq_MEMdq | PCMPEQB_XMMdq_XMMdq | PCMPEQD_MMXq_MEMq | PCMPEQD_MMXq_MMXq | PCMPEQD_XMMdq_MEMdq | PCMPEQD_XMMdq_XMMdq | PCMPEQQ_XMMdq_MEMdq | PCMPEQQ_XMMdq_XMMdq | PCMPEQW_MMXq_MEMq | PCMPEQW_MMXq_MMXq | PCMPEQW_XMMdq_MEMdq | PCMPEQW_XMMdq_XMMdq | PCMPESTRI_XMMdq_MEMdq_IMMb | PCMPESTRI_XMMdq_XMMdq_IMMb | PCMPESTRI64_XMMdq_MEMdq_IMMb | PCMPESTRI64_XMMdq_XMMdq_IMMb | PCMPESTRM_XMMdq_MEMdq_IMMb | PCMPESTRM_XMMdq_XMMdq_IMMb | PCMPESTRM64_XMMdq_MEMdq_IMMb | PCMPESTRM64_XMMdq_XMMdq_IMMb | PCMPGTB_MMXq_MEMq | PCMPGTB_MMXq_MMXq | PCMPGTB_XMMdq_MEMdq | PCMPGTB_XMMdq_XMMdq | PCMPGTD_MMXq_MEMq | PCMPGTD_MMXq_MMXq | PCMPGTD_XMMdq_MEMdq | PCMPGTD_XMMdq_XMMdq | PCMPGTQ_XMMdq_MEMdq | PCMPGTQ_XMMdq_XMMdq | PCMPGTW_MMXq_MEMq | PCMPGTW_MMXq_MMXq | PCMPGTW_XMMdq_MEMdq | PCMPGTW_XMMdq_XMMdq | PCMPISTRI_XMMdq_MEMdq_IMMb | PCMPISTRI_XMMdq_XMMdq_IMMb | PCMPISTRI64_XMMdq_MEMdq_IMMb | PCMPISTRI64_XMMdq_XMMdq_IMMb | PCMPISTRM_XMMdq_MEMdq_IMMb | PCMPISTRM_XMMdq_XMMdq_IMMb | PCONFIG | PCONFIG64 | PDEP_GPR32d_GPR32d_GPR32d | PDEP_GPR32d_GPR32d_MEMd | PDEP_GPR32i32_GPR32i32_GPR32i32_APX | PDEP_GPR32i32_GPR32i32_MEMi32_APX | PDEP_GPR64i64_GPR64i64_GPR64i64_APX | PDEP_GPR64i64_GPR64i64_MEMi64_APX | PDEP_GPR64q_GPR64q_GPR64q | PDEP_GPR64q_GPR64q_MEMq | PEXT_GPR32d_GPR32d_GPR32d | PEXT_GPR32d_GPR32d_MEMd | PEXT_GPR32i32_GPR32i32_GPR32i32_APX | PEXT_GPR32i32_GPR32i32_MEMi32_APX | PEXT_GPR64i64_GPR64i64_GPR64i64_APX | PEXT_GPR64i64_GPR64i64_MEMi64_APX | PEXT_GPR64q_GPR64q_GPR64q | PEXT_GPR64q_GPR64q_MEMq | PEXTRB_GPR32d_XMMdq_IMMb | PEXTRB_MEMb_XMMdq_IMMb | PEXTRD_GPR32d_XMMdq_IMMb | PEXTRD_MEMd_XMMdq_IMMb | PEXTRQ_GPR64q_XMMdq_IMMb | PEXTRQ_MEMq_XMMdq_IMMb | PEXTRW_GPR32_MMXq_IMMb | PEXTRW_GPR32_XMMdq_IMMb | PEXTRW_SSE4_GPR32_XMMdq_IMMb | PEXTRW_SSE4_MEMw_XMMdq_IMMb | PF2ID_MMXq_MEMq | PF2ID_MMXq_MMXq | PF2IW_MMXq_MEMq | PF2IW_MMXq_MMXq | PFACC_MMXq_MEMq | PFACC_MMXq_MMXq | PFADD_MMXq_MEMq | PFADD_MMXq_MMXq | PFCMPEQ_MMXq_MEMq | PFCMPEQ_MMXq_MMXq | PFCMPGE_MMXq_MEMq | PFCMPGE_MMXq_MMXq | PFCMPGT_MMXq_MEMq | PFCMPGT_MMXq_MMXq | PFMAX_MMXq_MEMq | PFMAX_MMXq_MMXq | PFMIN_MMXq_MEMq | PFMIN_MMXq_MMXq | PFMUL_MMXq_MEMq | PFMUL_MMXq_MMXq | PFNACC_MMXq_MEMq | PFNACC_MMXq_MMXq | PFPNACC_MMXq_MEMq | PFPNACC_MMXq_MMXq | PFRCP_MMXq_MEMq | PFRCP_MMXq_MMXq | PFRCPIT1_MMXq_MEMq | PFRCPIT1_MMXq_MMXq | PFRCPIT2_MMXq_MEMq | PFRCPIT2_MMXq_MMXq | PFRSQIT1_MMXq_MEMq | PFRSQIT1_MMXq_MMXq | PFRSQRT_MMXq_MEMq | PFRSQRT_MMXq_MMXq | PFSUB_MMXq_MEMq | PFSUB_MMXq_MMXq | PFSUBR_MMXq_MEMq | PFSUBR_MMXq_MMXq | PHADDD_MMXq_MEMq | PHADDD_MMXq_MMXq | PHADDD_XMMdq_MEMdq | PHADDD_XMMdq_XMMdq | PHADDSW_MMXq_MEMq | PHADDSW_MMXq_MMXq | PHADDSW_XMMdq_MEMdq | PHADDSW_XMMdq_XMMdq | PHADDW_MMXq_MEMq | PHADDW_MMXq_MMXq | PHADDW_XMMdq_MEMdq | PHADDW_XMMdq_XMMdq | PHMINPOSUW_XMMdq_MEMdq | PHMINPOSUW_XMMdq_XMMdq | PHSUBD_MMXq_MEMq | PHSUBD_MMXq_MMXq | PHSUBD_XMMdq_MEMdq | PHSUBD_XMMdq_XMMdq | PHSUBSW_MMXq_MEMq | PHSUBSW_MMXq_MMXq | PHSUBSW_XMMdq_MEMdq | PHSUBSW_XMMdq_XMMdq | PHSUBW_MMXq_MEMq | PHSUBW_MMXq_MMXq | PHSUBW_XMMdq_MEMdq | PHSUBW_XMMdq_XMMdq | PI2FD_MMXq_MEMq | PI2FD_MMXq_MMXq | PI2FW_MMXq_MEMq | PI2FW_MMXq_MMXq | PINSRB_XMMdq_GPR32d_IMMb | PINSRB_XMMdq_MEMb_IMMb | PINSRD_XMMdq_GPR32d_IMMb | PINSRD_XMMdq_MEMd_IMMb | PINSRQ_XMMdq_GPR64q_IMMb | PINSRQ_XMMdq_MEMq_IMMb | PINSRW_MMXq_GPR32_IMMb | PINSRW_MMXq_MEMw_IMMb | PINSRW_XMMdq_GPR32_IMMb | PINSRW_XMMdq_MEMw_IMMb | PMADDUBSW_MMXq_MEMq | PMADDUBSW_MMXq_MMXq | PMADDUBSW_XMMdq_MEMdq | PMADDUBSW_XMMdq_XMMdq | PMADDWD_MMXq_MEMq | PMADDWD_MMXq_MMXq | PMADDWD_XMMdq_MEMdq | PMADDWD_XMMdq_XMMdq | PMAXSB_XMMdq_MEMdq | PMAXSB_XMMdq_XMMdq | PMAXSD_XMMdq_MEMdq | PMAXSD_XMMdq_XMMdq | PMAXSW_MMXq_MEMq | PMAXSW_MMXq_MMXq | PMAXSW_XMMdq_MEMdq | PMAXSW_XMMdq_XMMdq | PMAXUB_MMXq_MEMq | PMAXUB_MMXq_MMXq | PMAXUB_XMMdq_MEMdq | PMAXUB_XMMdq_XMMdq | PMAXUD_XMMdq_MEMdq | PMAXUD_XMMdq_XMMdq | PMAXUW_XMMdq_MEMdq | PMAXUW_XMMdq_XMMdq | PMINSB_XMMdq_MEMdq | PMINSB_XMMdq_XMMdq | PMINSD_XMMdq_MEMdq | PMINSD_XMMdq_XMMdq | PMINSW_MMXq_MEMq | PMINSW_MMXq_MMXq | PMINSW_XMMdq_MEMdq | PMINSW_XMMdq_XMMdq | PMINUB_MMXq_MEMq | PMINUB_MMXq_MMXq | PMINUB_XMMdq_MEMdq | PMINUB_XMMdq_XMMdq | PMINUD_XMMdq_MEMdq | PMINUD_XMMdq_XMMdq | PMINUW_XMMdq_MEMdq | PMINUW_XMMdq_XMMdq | PMOVMSKB_GPR32_MMXq | PMOVMSKB_GPR32_XMMdq | PMOVSXBD_XMMdq_MEMd | PMOVSXBD_XMMdq_XMMd | PMOVSXBQ_XMMdq_MEMw | PMOVSXBQ_XMMdq_XMMw | PMOVSXBW_XMMdq_MEMq | PMOVSXBW_XMMdq_XMMq | PMOVSXDQ_XMMdq_MEMq | PMOVSXDQ_XMMdq_XMMq | PMOVSXWD_XMMdq_MEMq | PMOVSXWD_XMMdq_XMMq | PMOVSXWQ_XMMdq_MEMd | PMOVSXWQ_XMMdq_XMMd | PMOVZXBD_XMMdq_MEMd | PMOVZXBD_XMMdq_XMMd | PMOVZXBQ_XMMdq_MEMw | PMOVZXBQ_XMMdq_XMMw | PMOVZXBW_XMMdq_MEMq | PMOVZXBW_XMMdq_XMMq | PMOVZXDQ_XMMdq_MEMq | PMOVZXDQ_XMMdq_XMMq | PMOVZXWD_XMMdq_MEMq | PMOVZXWD_XMMdq_XMMq | PMOVZXWQ_XMMdq_MEMd | PMOVZXWQ_XMMdq_XMMd | PMULDQ_XMMdq_MEMdq | PMULDQ_XMMdq_XMMdq | PMULHRSW_MMXq_MEMq | PMULHRSW_MMXq_MMXq | PMULHRSW_XMMdq_MEMdq | PMULHRSW_XMMdq_XMMdq | PMULHRW_MMXq_MEMq | PMULHRW_MMXq_MMXq | PMULHUW_MMXq_MEMq | PMULHUW_MMXq_MMXq | PMULHUW_XMMdq_MEMdq | PMULHUW_XMMdq_XMMdq | PMULHW_MMXq_MEMq | PMULHW_MMXq_MMXq | PMULHW_XMMdq_MEMdq | PMULHW_XMMdq_XMMdq | PMULLD_XMMdq_MEMdq | PMULLD_XMMdq_XMMdq | PMULLW_MMXq_MEMq | PMULLW_MMXq_MMXq | PMULLW_XMMdq_MEMdq | PMULLW_XMMdq_XMMdq | PMULUDQ_MMXq_MEMq | PMULUDQ_MMXq_MMXq | PMULUDQ_XMMdq_MEMdq | PMULUDQ_XMMdq_XMMdq | POP_DS | POP_ES | POP_FS | POP_GPRv_58 | POP_GPRv_8F | POP_GS | POP_MEMv | POP_SS | POP2_GPR64u64_GPR64u64_APX | POP2P_GPR64u64_GPR64u64_APX | POPA | POPAD | POPCNT_GPRv_GPRv | POPCNT_GPRv_GPRv_APX | POPCNT_GPRv_MEMv | POPCNT_GPRv_MEMv_APX | POPF | POPFD | POPFQ | POPP_GPR64 | POR_MMXq_MEMq | POR_MMXq_MMXq | POR_XMMdq_MEMdq | POR_XMMdq_XMMdq | PREFETCHIT0_MEMu8 | PREFETCHIT1_MEMu8 | PREFETCHNTA_MEMmprefetch | PREFETCHT0_MEMmprefetch | PREFETCHT1_MEMmprefetch | PREFETCHT2_MEMmprefetch | PREFETCHW_0F0Dr1 | PREFETCHW_0F0Dr3 | PREFETCHWT1_MEMu8 | PREFETCH_EXCLUSIVE_MEMmprefetch | PREFETCH_RESERVED_0F0Dr4 | PREFETCH_RESERVED_0F0Dr5 | PREFETCH_RESERVED_0F0Dr6 | PREFETCH_RESERVED_0F0Dr7 | PSADBW_MMXq_MEMq | PSADBW_MMXq_MMXq | PSADBW_XMMdq_MEMdq | PSADBW_XMMdq_XMMdq | PSHUFB_MMXq_MEMq | PSHUFB_MMXq_MMXq | PSHUFB_XMMdq_MEMdq | PSHUFB_XMMdq_XMMdq | PSHUFD_XMMdq_MEMdq_IMMb | PSHUFD_XMMdq_XMMdq_IMMb | PSHUFHW_XMMdq_MEMdq_IMMb | PSHUFHW_XMMdq_XMMdq_IMMb | PSHUFLW_XMMdq_MEMdq_IMMb | PSHUFLW_XMMdq_XMMdq_IMMb | PSHUFW_MMXq_MEMq_IMMb | PSHUFW_MMXq_MMXq_IMMb | PSIGNB_MMXq_MEMq | PSIGNB_MMXq_MMXq | PSIGNB_XMMdq_MEMdq | PSIGNB_XMMdq_XMMdq | PSIGND_MMXq_MEMq | PSIGND_MMXq_MMXq | PSIGND_XMMdq_MEMdq | PSIGND_XMMdq_XMMdq | PSIGNW_MMXq_MEMq | PSIGNW_MMXq_MMXq | PSIGNW_XMMdq_MEMdq | PSIGNW_XMMdq_XMMdq | PSLLD_MMXq_IMMb | PSLLD_MMXq_MEMq | PSLLD_MMXq_MMXq | PSLLD_XMMdq_IMMb | PSLLD_XMMdq_MEMdq | PSLLD_XMMdq_XMMdq | PSLLDQ_XMMdq_IMMb | PSLLQ_MMXq_IMMb | PSLLQ_MMXq_MEMq | PSLLQ_MMXq_MMXq | PSLLQ_XMMdq_IMMb | PSLLQ_XMMdq_MEMdq | PSLLQ_XMMdq_XMMdq | PSLLW_MMXq_IMMb | PSLLW_MMXq_MEMq | PSLLW_MMXq_MMXq | PSLLW_XMMdq_IMMb | PSLLW_XMMdq_MEMdq | PSLLW_XMMdq_XMMdq | PSMASH_RAX | PSRAD_MMXq_IMMb | PSRAD_MMXq_MEMq | PSRAD_MMXq_MMXq | PSRAD_XMMdq_IMMb | PSRAD_XMMdq_MEMdq | PSRAD_XMMdq_XMMdq | PSRAW_MMXq_IMMb | PSRAW_MMXq_MEMq | PSRAW_MMXq_MMXq | PSRAW_XMMdq_IMMb | PSRAW_XMMdq_MEMdq | PSRAW_XMMdq_XMMdq | PSRLD_MMXq_IMMb | PSRLD_MMXq_MEMq | PSRLD_MMXq_MMXq | PSRLD_XMMdq_IMMb | PSRLD_XMMdq_MEMdq | PSRLD_XMMdq_XMMdq | PSRLDQ_XMMdq_IMMb | PSRLQ_MMXq_IMMb | PSRLQ_MMXq_MEMq | PSRLQ_MMXq_MMXq | PSRLQ_XMMdq_IMMb | PSRLQ_XMMdq_MEMdq | PSRLQ_XMMdq_XMMdq | PSRLW_MMXq_IMMb | PSRLW_MMXq_MEMq | PSRLW_MMXq_MMXq | PSRLW_XMMdq_IMMb | PSRLW_XMMdq_MEMdq | PSRLW_XMMdq_XMMdq | PSUBB_MMXq_MEMq | PSUBB_MMXq_MMXq | PSUBB_XMMdq_MEMdq | PSUBB_XMMdq_XMMdq | PSUBD_MMXq_MEMq | PSUBD_MMXq_MMXq | PSUBD_XMMdq_MEMdq | PSUBD_XMMdq_XMMdq | PSUBQ_MMXq_MEMq | PSUBQ_MMXq_MMXq | PSUBQ_XMMdq_MEMdq | PSUBQ_XMMdq_XMMdq | PSUBSB_MMXq_MEMq | PSUBSB_MMXq_MMXq | PSUBSB_XMMdq_MEMdq | PSUBSB_XMMdq_XMMdq | PSUBSW_MMXq_MEMq | PSUBSW_MMXq_MMXq | PSUBSW_XMMdq_MEMdq | PSUBSW_XMMdq_XMMdq | PSUBUSB_MMXq_MEMq | PSUBUSB_MMXq_MMXq | PSUBUSB_XMMdq_MEMdq | PSUBUSB_XMMdq_XMMdq | PSUBUSW_MMXq_MEMq | PSUBUSW_MMXq_MMXq | PSUBUSW_XMMdq_MEMdq | PSUBUSW_XMMdq_XMMdq | PSUBW_MMXq_MEMq | PSUBW_MMXq_MMXq | PSUBW_XMMdq_MEMdq | PSUBW_XMMdq_XMMdq | PSWAPD_MMXq_MEMq | PSWAPD_MMXq_MMXq | PTEST_XMMdq_MEMdq | PTEST_XMMdq_XMMdq | PTWRITE_GPRy | PTWRITE_MEMy | PUNPCKHBW_MMXq_MEMq | PUNPCKHBW_MMXq_MMXd | PUNPCKHBW_XMMdq_MEMdq | PUNPCKHBW_XMMdq_XMMq | PUNPCKHDQ_MMXq_MEMq | PUNPCKHDQ_MMXq_MMXd | PUNPCKHDQ_XMMdq_MEMdq | PUNPCKHDQ_XMMdq_XMMq | PUNPCKHQDQ_XMMdq_MEMdq | PUNPCKHQDQ_XMMdq_XMMq | PUNPCKHWD_MMXq_MEMq | PUNPCKHWD_MMXq_MMXd | PUNPCKHWD_XMMdq_MEMdq | PUNPCKHWD_XMMdq_XMMq | PUNPCKLBW_MMXq_MEMd | PUNPCKLBW_MMXq_MMXd | PUNPCKLBW_XMMdq_MEMdq | PUNPCKLBW_XMMdq_XMMq | PUNPCKLDQ_MMXq_MEMd | PUNPCKLDQ_MMXq_MMXd | PUNPCKLDQ_XMMdq_MEMdq | PUNPCKLDQ_XMMdq_XMMq | PUNPCKLQDQ_XMMdq_MEMdq | PUNPCKLQDQ_XMMdq_XMMq | PUNPCKLWD_MMXq_MEMd | PUNPCKLWD_MMXq_MMXd | PUNPCKLWD_XMMdq_MEMdq | PUNPCKLWD_XMMdq_XMMq | PUSH_CS | PUSH_DS | PUSH_ES | PUSH_FS | PUSH_GPRv_50 | PUSH_GPRv_FFr6 | PUSH_GS | PUSH_IMMb | PUSH_IMMz | PUSH_MEMv | PUSH_SS | PUSH2_GPR64u64_GPR64u64_APX | PUSH2P_GPR64u64_GPR64u64_APX | PUSHA | PUSHAD | PUSHF | PUSHFD | PUSHFQ | PUSHP_GPR64 | PVALIDATE_RAX_ECX_EDX | PXOR_MMXq_MEMq | PXOR_MMXq_MMXq | PXOR_XMMdq_MEMdq | PXOR_XMMdq_XMMdq | RCL_GPR8_CL | RCL_GPR8_IMMb | RCL_GPR8_ONE | RCL_GPR8i8_CL_APX | RCL_GPR8i8_GPR8i8_CL_APX | RCL_GPR8i8_GPR8i8_IMM8_APX | RCL_GPR8i8_GPR8i8_ONE_APX | RCL_GPR8i8_IMM8_APX | RCL_GPR8i8_MEMi8_CL_APX | RCL_GPR8i8_MEMi8_IMM8_APX | RCL_GPR8i8_MEMi8_ONE_APX | RCL_GPR8i8_ONE_APX | RCL_GPRv_CL | RCL_GPRv_CL_APX | RCL_GPRv_GPRv_CL_APX | RCL_GPRv_GPRv_IMM8_APX | RCL_GPRv_GPRv_ONE_APX | RCL_GPRv_IMM8_APX | RCL_GPRv_IMMb | RCL_GPRv_MEMv_CL_APX | RCL_GPRv_MEMv_IMM8_APX | RCL_GPRv_MEMv_ONE_APX | RCL_GPRv_ONE | RCL_GPRv_ONE_APX | RCL_MEMb_CL | RCL_MEMb_IMMb | RCL_MEMb_ONE | RCL_MEMi8_CL_APX | RCL_MEMi8_IMM8_APX | RCL_MEMi8_ONE_APX | RCL_MEMv_CL | RCL_MEMv_CL_APX | RCL_MEMv_IMM8_APX | RCL_MEMv_IMMb | RCL_MEMv_ONE | RCL_MEMv_ONE_APX | RCPPS_XMMps_MEMps | RCPPS_XMMps_XMMps | RCPSS_XMMss_MEMss | RCPSS_XMMss_XMMss | RCR_GPR8_CL | RCR_GPR8_IMMb | RCR_GPR8_ONE | RCR_GPR8i8_CL_APX | RCR_GPR8i8_GPR8i8_CL_APX | RCR_GPR8i8_GPR8i8_IMM8_APX | RCR_GPR8i8_GPR8i8_ONE_APX | RCR_GPR8i8_IMM8_APX | RCR_GPR8i8_MEMi8_CL_APX | RCR_GPR8i8_MEMi8_IMM8_APX | RCR_GPR8i8_MEMi8_ONE_APX | RCR_GPR8i8_ONE_APX | RCR_GPRv_CL | RCR_GPRv_CL_APX | RCR_GPRv_GPRv_CL_APX | RCR_GPRv_GPRv_IMM8_APX | RCR_GPRv_GPRv_ONE_APX | RCR_GPRv_IMM8_APX | RCR_GPRv_IMMb | RCR_GPRv_MEMv_CL_APX | RCR_GPRv_MEMv_IMM8_APX | RCR_GPRv_MEMv_ONE_APX | RCR_GPRv_ONE | RCR_GPRv_ONE_APX | RCR_MEMb_CL | RCR_MEMb_IMMb | RCR_MEMb_ONE | RCR_MEMi8_CL_APX | RCR_MEMi8_IMM8_APX | RCR_MEMi8_ONE_APX | RCR_MEMv_CL | RCR_MEMv_CL_APX | RCR_MEMv_IMM8_APX | RCR_MEMv_IMMb | RCR_MEMv_ONE | RCR_MEMv_ONE_APX | RDFSBASE_GPRy | RDGSBASE_GPRy | RDMSR | RDMSRLIST | RDPID_GPR32u32 | RDPID_GPR64u64 | RDPKRU | RDPMC | RDPRU | RDRAND_GPRv | RDSEED_GPRv | RDSSPD_GPR32u32 | RDSSPQ_GPR64u64 | RDTSC | RDTSCP | REPE_CMPSB | REPE_CMPSD | REPE_CMPSQ | REPE_CMPSW | REPE_SCASB | REPE_SCASD | REPE_SCASQ | REPE_SCASW | REPNE_CMPSB | REPNE_CMPSD | REPNE_CMPSQ | REPNE_CMPSW | REPNE_SCASB | REPNE_SCASD | REPNE_SCASQ | REPNE_SCASW | REP_INSB | REP_INSD | REP_INSW | REP_LODSB | REP_LODSD | REP_LODSQ | REP_LODSW | REP_MONTMUL | REP_MOVSB | REP_MOVSD | REP_MOVSQ | REP_MOVSW | REP_OUTSB | REP_OUTSD | REP_OUTSW | REP_STOSB | REP_STOSD | REP_STOSQ | REP_STOSW | REP_XCRYPTCBC | REP_XCRYPTCFB | REP_XCRYPTCTR | REP_XCRYPTECB | REP_XCRYPTOFB | REP_XSHA1 | REP_XSHA256 | REP_XSTORE | RET_FAR | RET_FAR_IMMw | RET_NEAR | RET_NEAR_IMMw | RMPADJUST_RAX_RCX_RDX | RMPUPDATE_RAX_RCX | ROL_GPR8_CL | ROL_GPR8_IMMb | ROL_GPR8_ONE | ROL_GPR8i8_CL_APX | ROL_GPR8i8_GPR8i8_CL_APX | ROL_GPR8i8_GPR8i8_IMM8_APX | ROL_GPR8i8_GPR8i8_ONE_APX | ROL_GPR8i8_IMM8_APX | ROL_GPR8i8_MEMi8_CL_APX | ROL_GPR8i8_MEMi8_IMM8_APX | ROL_GPR8i8_MEMi8_ONE_APX | ROL_GPR8i8_ONE_APX | ROL_GPRv_CL | ROL_GPRv_CL_APX | ROL_GPRv_GPRv_CL_APX | ROL_GPRv_GPRv_IMM8_APX | ROL_GPRv_GPRv_ONE_APX | ROL_GPRv_IMM8_APX | ROL_GPRv_IMMb | ROL_GPRv_MEMv_CL_APX | ROL_GPRv_MEMv_IMM8_APX | ROL_GPRv_MEMv_ONE_APX | ROL_GPRv_ONE | ROL_GPRv_ONE_APX | ROL_MEMb_CL | ROL_MEMb_IMMb | ROL_MEMb_ONE | ROL_MEMi8_CL_APX | ROL_MEMi8_IMM8_APX | ROL_MEMi8_ONE_APX | ROL_MEMv_CL | ROL_MEMv_CL_APX | ROL_MEMv_IMM8_APX | ROL_MEMv_IMMb | ROL_MEMv_ONE | ROL_MEMv_ONE_APX | ROR_GPR8_CL | ROR_GPR8_IMMb | ROR_GPR8_ONE | ROR_GPR8i8_CL_APX | ROR_GPR8i8_GPR8i8_CL_APX | ROR_GPR8i8_GPR8i8_IMM8_APX | ROR_GPR8i8_GPR8i8_ONE_APX | ROR_GPR8i8_IMM8_APX | ROR_GPR8i8_MEMi8_CL_APX | ROR_GPR8i8_MEMi8_IMM8_APX | ROR_GPR8i8_MEMi8_ONE_APX | ROR_GPR8i8_ONE_APX | ROR_GPRv_CL | ROR_GPRv_CL_APX | ROR_GPRv_GPRv_CL_APX | ROR_GPRv_GPRv_IMM8_APX | ROR_GPRv_GPRv_ONE_APX | ROR_GPRv_IMM8_APX | ROR_GPRv_IMMb | ROR_GPRv_MEMv_CL_APX | ROR_GPRv_MEMv_IMM8_APX | ROR_GPRv_MEMv_ONE_APX | ROR_GPRv_ONE | ROR_GPRv_ONE_APX | ROR_MEMb_CL | ROR_MEMb_IMMb | ROR_MEMb_ONE | ROR_MEMi8_CL_APX | ROR_MEMi8_IMM8_APX | ROR_MEMi8_ONE_APX | ROR_MEMv_CL | ROR_MEMv_CL_APX | ROR_MEMv_IMM8_APX | ROR_MEMv_IMMb | ROR_MEMv_ONE | ROR_MEMv_ONE_APX | RORX_GPR32d_GPR32d_IMMb | RORX_GPR32d_MEMd_IMMb | RORX_GPR32i32_GPR32i32_IMM8_APX | RORX_GPR32i32_MEMi32_IMM8_APX | RORX_GPR64i64_GPR64i64_IMM8_APX | RORX_GPR64i64_MEMi64_IMM8_APX | RORX_GPR64q_GPR64q_IMMb | RORX_GPR64q_MEMq_IMMb | ROUNDPD_XMMpd_MEMpd_IMMb | ROUNDPD_XMMpd_XMMpd_IMMb | ROUNDPS_XMMps_MEMps_IMMb | ROUNDPS_XMMps_XMMps_IMMb | ROUNDSD_XMMq_MEMq_IMMb | ROUNDSD_XMMq_XMMq_IMMb | ROUNDSS_XMMd_MEMd_IMMb | ROUNDSS_XMMd_XMMd_IMMb | RSM | RSQRTPS_XMMps_MEMps | RSQRTPS_XMMps_XMMps | RSQRTSS_XMMss_MEMss | RSQRTSS_XMMss_XMMss | RSTORSSP_MEMu64 | SAHF | SALC | SAR_GPR8_CL | SAR_GPR8_IMMb | SAR_GPR8_ONE | SAR_GPR8i8_CL_APX | SAR_GPR8i8_GPR8i8_CL_APX | SAR_GPR8i8_GPR8i8_IMM8_APX | SAR_GPR8i8_GPR8i8_ONE_APX | SAR_GPR8i8_IMM8_APX | SAR_GPR8i8_MEMi8_CL_APX | SAR_GPR8i8_MEMi8_IMM8_APX | SAR_GPR8i8_MEMi8_ONE_APX | SAR_GPR8i8_ONE_APX | SAR_GPRv_CL | SAR_GPRv_CL_APX | SAR_GPRv_GPRv_CL_APX | SAR_GPRv_GPRv_IMM8_APX | SAR_GPRv_GPRv_ONE_APX | SAR_GPRv_IMM8_APX | SAR_GPRv_IMMb | SAR_GPRv_MEMv_CL_APX | SAR_GPRv_MEMv_IMM8_APX | SAR_GPRv_MEMv_ONE_APX | SAR_GPRv_ONE | SAR_GPRv_ONE_APX | SAR_MEMb_CL | SAR_MEMb_IMMb | SAR_MEMb_ONE | SAR_MEMi8_CL_APX | SAR_MEMi8_IMM8_APX | SAR_MEMi8_ONE_APX | SAR_MEMv_CL | SAR_MEMv_CL_APX | SAR_MEMv_IMM8_APX | SAR_MEMv_IMMb | SAR_MEMv_ONE | SAR_MEMv_ONE_APX | SARX_GPR32d_GPR32d_GPR32d | SARX_GPR32d_MEMd_GPR32d | SARX_GPR32i32_GPR32i32_GPR32i32_APX | SARX_GPR32i32_MEMi32_GPR32i32_APX | SARX_GPR64i64_GPR64i64_GPR64i64_APX | SARX_GPR64i64_MEMi64_GPR64i64_APX | SARX_GPR64q_GPR64q_GPR64q | SARX_GPR64q_MEMq_GPR64q | SAVEPREVSSP | SBB_AL_IMMb | SBB_GPR8_GPR8_18 | SBB_GPR8_GPR8_1A | SBB_GPR8_IMMb_80r3 | SBB_GPR8_IMMb_82r3 | SBB_GPR8_MEMb | SBB_GPR8i8_GPR8i8_APX | SBB_GPR8i8_GPR8i8_GPR8i8_APX | SBB_GPR8i8_GPR8i8_IMM8_APX | SBB_GPR8i8_GPR8i8_MEMi8_APX | SBB_GPR8i8_IMM8_APX | SBB_GPR8i8_MEMi8_APX | SBB_GPR8i8_MEMi8_GPR8i8_APX | SBB_GPR8i8_MEMi8_IMM8_APX | SBB_GPRv_GPRv_19 | SBB_GPRv_GPRv_1B | SBB_GPRv_GPRv_APX | SBB_GPRv_GPRv_GPRv_APX | SBB_GPRv_GPRv_IMM8_APX | SBB_GPRv_GPRv_IMMz_APX | SBB_GPRv_GPRv_MEMv_APX | SBB_GPRv_IMM8_APX | SBB_GPRv_IMMb | SBB_GPRv_IMMz | SBB_GPRv_IMMz_APX | SBB_GPRv_MEMv | SBB_GPRv_MEMv_APX | SBB_GPRv_MEMv_GPRv_APX | SBB_GPRv_MEMv_IMM8_APX | SBB_GPRv_MEMv_IMMz_APX | SBB_MEMb_GPR8 | SBB_MEMb_IMMb_80r3 | SBB_MEMb_IMMb_82r3 | SBB_MEMi8_GPR8i8_APX | SBB_MEMi8_IMM8_APX | SBB_MEMv_GPRv | SBB_MEMv_GPRv_APX | SBB_MEMv_IMM8_APX | SBB_MEMv_IMMb | SBB_MEMv_IMMz | SBB_MEMv_IMMz_APX | SBB_OrAX_IMMz | SBB_LOCK_MEMb_GPR8 | SBB_LOCK_MEMb_IMMb_80r3 | SBB_LOCK_MEMb_IMMb_82r3 | SBB_LOCK_MEMv_GPRv | SBB_LOCK_MEMv_IMMb | SBB_LOCK_MEMv_IMMz | SCASB | SCASD | SCASQ | SCASW | SEAMCALL | SEAMOPS | SEAMRET | SENDUIPI_GPR64u32 | SERIALIZE | SETB_GPR8 | SETB_GPR8i8_APX | SETB_GPR8i8_APX_ZU | SETB_MEMb | SETB_MEMi8_APX | SETB_MEMi8_APX_ZU | SETBE_GPR8 | SETBE_GPR8i8_APX | SETBE_GPR8i8_APX_ZU | SETBE_MEMb | SETBE_MEMi8_APX | SETBE_MEMi8_APX_ZU | SETL_GPR8 | SETL_GPR8i8_APX | SETL_GPR8i8_APX_ZU | SETL_MEMb | SETL_MEMi8_APX | SETL_MEMi8_APX_ZU | SETLE_GPR8 | SETLE_GPR8i8_APX | SETLE_GPR8i8_APX_ZU | SETLE_MEMb | SETLE_MEMi8_APX | SETLE_MEMi8_APX_ZU | SETNB_GPR8 | SETNB_GPR8i8_APX | SETNB_GPR8i8_APX_ZU | SETNB_MEMb | SETNB_MEMi8_APX | SETNB_MEMi8_APX_ZU | SETNBE_GPR8 | SETNBE_GPR8i8_APX | SETNBE_GPR8i8_APX_ZU | SETNBE_MEMb | SETNBE_MEMi8_APX | SETNBE_MEMi8_APX_ZU | SETNL_GPR8 | SETNL_GPR8i8_APX | SETNL_GPR8i8_APX_ZU | SETNL_MEMb | SETNL_MEMi8_APX | SETNL_MEMi8_APX_ZU | SETNLE_GPR8 | SETNLE_GPR8i8_APX | SETNLE_GPR8i8_APX_ZU | SETNLE_MEMb | SETNLE_MEMi8_APX | SETNLE_MEMi8_APX_ZU | SETNO_GPR8 | SETNO_GPR8i8_APX | SETNO_GPR8i8_APX_ZU | SETNO_MEMb | SETNO_MEMi8_APX | SETNO_MEMi8_APX_ZU | SETNP_GPR8 | SETNP_GPR8i8_APX | SETNP_GPR8i8_APX_ZU | SETNP_MEMb | SETNP_MEMi8_APX | SETNP_MEMi8_APX_ZU | SETNS_GPR8 | SETNS_GPR8i8_APX | SETNS_GPR8i8_APX_ZU | SETNS_MEMb | SETNS_MEMi8_APX | SETNS_MEMi8_APX_ZU | SETNZ_GPR8 | SETNZ_GPR8i8_APX | SETNZ_GPR8i8_APX_ZU | SETNZ_MEMb | SETNZ_MEMi8_APX | SETNZ_MEMi8_APX_ZU | SETO_GPR8 | SETO_GPR8i8_APX | SETO_GPR8i8_APX_ZU | SETO_MEMb | SETO_MEMi8_APX | SETO_MEMi8_APX_ZU | SETP_GPR8 | SETP_GPR8i8_APX | SETP_GPR8i8_APX_ZU | SETP_MEMb | SETP_MEMi8_APX | SETP_MEMi8_APX_ZU | SETS_GPR8 | SETS_GPR8i8_APX | SETS_GPR8i8_APX_ZU | SETS_MEMb | SETS_MEMi8_APX | SETS_MEMi8_APX_ZU | SETSSBSY | SETZ_GPR8 | SETZ_GPR8i8_APX | SETZ_GPR8i8_APX_ZU | SETZ_MEMb | SETZ_MEMi8_APX | SETZ_MEMi8_APX_ZU | SFENCE | SGDT_MEMs | SGDT_MEMs64 | SHA1MSG1_XMMi32_MEMi32_SHA | SHA1MSG1_XMMi32_XMMi32_SHA | SHA1MSG2_XMMi32_MEMi32_SHA | SHA1MSG2_XMMi32_XMMi32_SHA | SHA1NEXTE_XMMi32_MEMi32_SHA | SHA1NEXTE_XMMi32_XMMi32_SHA | SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA | SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA | SHA256MSG1_XMMi32_MEMi32_SHA | SHA256MSG1_XMMi32_XMMi32_SHA | SHA256MSG2_XMMi32_MEMi32_SHA | SHA256MSG2_XMMi32_XMMi32_SHA | SHA256RNDS2_XMMi32_MEMi32_SHA | SHA256RNDS2_XMMi32_XMMi32_SHA | SHL_GPR8_CL_D2r4 | SHL_GPR8_CL_D2r6 | SHL_GPR8_IMMb_C0r4 | SHL_GPR8_IMMb_C0r6 | SHL_GPR8_ONE_D0r4 | SHL_GPR8_ONE_D0r6 | SHL_GPR8i8_CL_APX | SHL_GPR8i8_GPR8i8_CL_APX | SHL_GPR8i8_GPR8i8_IMM8_APX | SHL_GPR8i8_GPR8i8_ONE_APX | SHL_GPR8i8_IMM8_APX | SHL_GPR8i8_MEMi8_CL_APX | SHL_GPR8i8_MEMi8_IMM8_APX | SHL_GPR8i8_MEMi8_ONE_APX | SHL_GPR8i8_ONE_APX | SHL_GPRv_CL_APX | SHL_GPRv_CL_D3r4 | SHL_GPRv_CL_D3r6 | SHL_GPRv_GPRv_CL_APX | SHL_GPRv_GPRv_IMM8_APX | SHL_GPRv_GPRv_ONE_APX | SHL_GPRv_IMM8_APX | SHL_GPRv_IMMb_C1r4 | SHL_GPRv_IMMb_C1r6 | SHL_GPRv_MEMv_CL_APX | SHL_GPRv_MEMv_IMM8_APX | SHL_GPRv_MEMv_ONE_APX | SHL_GPRv_ONE_APX | SHL_GPRv_ONE_D1r4 | SHL_GPRv_ONE_D1r6 | SHL_MEMb_CL_D2r4 | SHL_MEMb_CL_D2r6 | SHL_MEMb_IMMb_C0r4 | SHL_MEMb_IMMb_C0r6 | SHL_MEMb_ONE_D0r4 | SHL_MEMb_ONE_D0r6 | SHL_MEMi8_CL_APX | SHL_MEMi8_IMM8_APX | SHL_MEMi8_ONE_APX | SHL_MEMv_CL_APX | SHL_MEMv_CL_D3r4 | SHL_MEMv_CL_D3r6 | SHL_MEMv_IMM8_APX | SHL_MEMv_IMMb_C1r4 | SHL_MEMv_IMMb_C1r6 | SHL_MEMv_ONE_APX | SHL_MEMv_ONE_D1r4 | SHL_MEMv_ONE_D1r6 | SHLD_GPRv_GPRv_CL | SHLD_GPRv_GPRv_CL_APX | SHLD_GPRv_GPRv_GPRv_CL_APX | SHLD_GPRv_GPRv_GPRv_IMM8_APX | SHLD_GPRv_GPRv_IMM8_APX | SHLD_GPRv_GPRv_IMMb | SHLD_GPRv_MEMv_GPRv_CL_APX | SHLD_GPRv_MEMv_GPRv_IMM8_APX | SHLD_MEMv_GPRv_CL | SHLD_MEMv_GPRv_CL_APX | SHLD_MEMv_GPRv_IMM8_APX | SHLD_MEMv_GPRv_IMMb | SHLX_GPR32d_GPR32d_GPR32d | SHLX_GPR32d_MEMd_GPR32d | SHLX_GPR32i32_GPR32i32_GPR32i32_APX | SHLX_GPR32i32_MEMi32_GPR32i32_APX | SHLX_GPR64i64_GPR64i64_GPR64i64_APX | SHLX_GPR64i64_MEMi64_GPR64i64_APX | SHLX_GPR64q_GPR64q_GPR64q | SHLX_GPR64q_MEMq_GPR64q | SHR_GPR8_CL | SHR_GPR8_IMMb | SHR_GPR8_ONE | SHR_GPR8i8_CL_APX | SHR_GPR8i8_GPR8i8_CL_APX | SHR_GPR8i8_GPR8i8_IMM8_APX | SHR_GPR8i8_GPR8i8_ONE_APX | SHR_GPR8i8_IMM8_APX | SHR_GPR8i8_MEMi8_CL_APX | SHR_GPR8i8_MEMi8_IMM8_APX | SHR_GPR8i8_MEMi8_ONE_APX | SHR_GPR8i8_ONE_APX | SHR_GPRv_CL | SHR_GPRv_CL_APX | SHR_GPRv_GPRv_CL_APX | SHR_GPRv_GPRv_IMM8_APX | SHR_GPRv_GPRv_ONE_APX | SHR_GPRv_IMM8_APX | SHR_GPRv_IMMb | SHR_GPRv_MEMv_CL_APX | SHR_GPRv_MEMv_IMM8_APX | SHR_GPRv_MEMv_ONE_APX | SHR_GPRv_ONE | SHR_GPRv_ONE_APX | SHR_MEMb_CL | SHR_MEMb_IMMb | SHR_MEMb_ONE | SHR_MEMi8_CL_APX | SHR_MEMi8_IMM8_APX | SHR_MEMi8_ONE_APX | SHR_MEMv_CL | SHR_MEMv_CL_APX | SHR_MEMv_IMM8_APX | SHR_MEMv_IMMb | SHR_MEMv_ONE | SHR_MEMv_ONE_APX | SHRD_GPRv_GPRv_CL | SHRD_GPRv_GPRv_CL_APX | SHRD_GPRv_GPRv_GPRv_CL_APX | SHRD_GPRv_GPRv_GPRv_IMM8_APX | SHRD_GPRv_GPRv_IMM8_APX | SHRD_GPRv_GPRv_IMMb | SHRD_GPRv_MEMv_GPRv_CL_APX | SHRD_GPRv_MEMv_GPRv_IMM8_APX | SHRD_MEMv_GPRv_CL | SHRD_MEMv_GPRv_CL_APX | SHRD_MEMv_GPRv_IMM8_APX | SHRD_MEMv_GPRv_IMMb | SHRX_GPR32d_GPR32d_GPR32d | SHRX_GPR32d_MEMd_GPR32d | SHRX_GPR32i32_GPR32i32_GPR32i32_APX | SHRX_GPR32i32_MEMi32_GPR32i32_APX | SHRX_GPR64i64_GPR64i64_GPR64i64_APX | SHRX_GPR64i64_MEMi64_GPR64i64_APX | SHRX_GPR64q_GPR64q_GPR64q | SHRX_GPR64q_MEMq_GPR64q | SHUFPD_XMMpd_MEMpd_IMMb | SHUFPD_XMMpd_XMMpd_IMMb | SHUFPS_XMMps_MEMps_IMMb | SHUFPS_XMMps_XMMps_IMMb | SIDT_MEMs | SIDT_MEMs64 | SKINIT_EAX | SLDT_GPRv | SLDT_MEMw | SLWPCB_GPRyy | SMSW_GPRv | SMSW_MEMw | SQRTPD_XMMpd_MEMpd | SQRTPD_XMMpd_XMMpd | SQRTPS_XMMps_MEMps | SQRTPS_XMMps_XMMps | SQRTSD_XMMsd_MEMsd | SQRTSD_XMMsd_XMMsd | SQRTSS_XMMss_MEMss | SQRTSS_XMMss_XMMss | STAC | STC | STD | STGI | STI | STMXCSR_MEMd | STOSB | STOSD | STOSQ | STOSW | STR_GPRv | STR_MEMw | STTILECFG_MEM | STTILECFG_MEM_APX | STUI | SUB_AL_IMMb | SUB_GPR8_GPR8_28 | SUB_GPR8_GPR8_2A | SUB_GPR8_IMMb_80r5 | SUB_GPR8_IMMb_82r5 | SUB_GPR8_MEMb | SUB_GPR8i8_GPR8i8_APX | SUB_GPR8i8_GPR8i8_GPR8i8_APX | SUB_GPR8i8_GPR8i8_IMM8_APX | SUB_GPR8i8_GPR8i8_MEMi8_APX | SUB_GPR8i8_IMM8_APX | SUB_GPR8i8_MEMi8_APX | SUB_GPR8i8_MEMi8_GPR8i8_APX | SUB_GPR8i8_MEMi8_IMM8_APX | SUB_GPRv_GPRv_29 | SUB_GPRv_GPRv_2B | SUB_GPRv_GPRv_APX | SUB_GPRv_GPRv_GPRv_APX | SUB_GPRv_GPRv_IMM8_APX | SUB_GPRv_GPRv_IMMz_APX | SUB_GPRv_GPRv_MEMv_APX | SUB_GPRv_IMM8_APX | SUB_GPRv_IMMb | SUB_GPRv_IMMz | SUB_GPRv_IMMz_APX | SUB_GPRv_MEMv | SUB_GPRv_MEMv_APX | SUB_GPRv_MEMv_GPRv_APX | SUB_GPRv_MEMv_IMM8_APX | SUB_GPRv_MEMv_IMMz_APX | SUB_MEMb_GPR8 | SUB_MEMb_IMMb_80r5 | SUB_MEMb_IMMb_82r5 | SUB_MEMi8_GPR8i8_APX | SUB_MEMi8_IMM8_APX | SUB_MEMv_GPRv | SUB_MEMv_GPRv_APX | SUB_MEMv_IMM8_APX | SUB_MEMv_IMMb | SUB_MEMv_IMMz | SUB_MEMv_IMMz_APX | SUB_OrAX_IMMz | SUBPD_XMMpd_MEMpd | SUBPD_XMMpd_XMMpd | SUBPS_XMMps_MEMps | SUBPS_XMMps_XMMps | SUBSD_XMMsd_MEMsd | SUBSD_XMMsd_XMMsd | SUBSS_XMMss_MEMss | SUBSS_XMMss_XMMss | SUB_LOCK_MEMb_GPR8 | SUB_LOCK_MEMb_IMMb_80r5 | SUB_LOCK_MEMb_IMMb_82r5 | SUB_LOCK_MEMv_GPRv | SUB_LOCK_MEMv_IMMb | SUB_LOCK_MEMv_IMMz | SWAPGS | SYSCALL | SYSCALL_32 | SYSENTER | SYSEXIT | SYSRET | SYSRET64 | SYSRET_AMD | T1MSKC_GPR32d_GPR32d | T1MSKC_GPR32d_MEMd | T1MSKC_GPRyy_GPRyy | T1MSKC_GPRyy_MEMy | TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 | TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 | TDCALL | TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16 | TDPBSSD_TMMi32_TMM4i8_TMM4i8 | TDPBSUD_TMMi32_TMM4i8_TMM4u8 | TDPBUSD_TMMi32_TMM4u8_TMM4i8 | TDPBUUD_TMMu32_TMM4u8_TMM4u8 | TDPFP16PS_TMMf32_TMM2f16_TMM2f16 | TEST_AL_IMMb | TEST_GPR8_GPR8 | TEST_GPR8_IMMb_F6r0 | TEST_GPR8_IMMb_F6r1 | TEST_GPRv_GPRv | TEST_GPRv_IMMz_F7r0 | TEST_GPRv_IMMz_F7r1 | TEST_MEMb_GPR8 | TEST_MEMb_IMMb_F6r0 | TEST_MEMb_IMMb_F6r1 | TEST_MEMv_GPRv | TEST_MEMv_IMMz_F7r0 | TEST_MEMv_IMMz_F7r1 | TEST_OrAX_IMMz | TESTUI | TILELOADD_TMMu32_MEMu32 | TILELOADD_TMMu32_MEMu32_APX | TILELOADDT1_TMMu32_MEMu32 | TILELOADDT1_TMMu32_MEMu32_APX | TILERELEASE | TILESTORED_MEMu32_TMMu32 | TILESTORED_MEMu32_TMMu32_APX | TILEZERO_TMMu32 | TLBSYNC | TPAUSE_GPR32u32 | TZCNT_GPRv_GPRv | TZCNT_GPRv_GPRv_APX | TZCNT_GPRv_MEMv | TZCNT_GPRv_MEMv_APX | TZMSK_GPR32d_GPR32d | TZMSK_GPR32d_MEMd | TZMSK_GPRyy_GPRyy | TZMSK_GPRyy_MEMy | UCOMISD_XMMsd_MEMsd | UCOMISD_XMMsd_XMMsd | UCOMISS_XMMss_MEMss | UCOMISS_XMMss_XMMss | UD0 | UD0_GPR32_GPR32 | UD0_GPR32_MEMd | UD1_GPR32_GPR32 | UD1_GPR32_MEMd | UD2 | UIRET | UMONITOR_GPRa | UMWAIT_GPR32 | UNPCKHPD_XMMpd_MEMdq | UNPCKHPD_XMMpd_XMMq | UNPCKHPS_XMMps_MEMdq | UNPCKHPS_XMMps_XMMdq | UNPCKLPD_XMMpd_MEMdq | UNPCKLPD_XMMpd_XMMq | UNPCKLPS_XMMps_MEMdq | UNPCKLPS_XMMps_XMMq | URDMSR_GPR64u64_GPR64u64 | URDMSR_GPR64u64_GPR64u64_APX | URDMSR_GPR64u64_IMM32 | URDMSR_GPR64u64_IMM32_APX | UWRMSR_GPR64u64_GPR64u64 | UWRMSR_GPR64u64_GPR64u64_APX | UWRMSR_IMM32_GPR64u64 | UWRMSR_IMM32_GPR64u64_APX | V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VADDPD_XMMdq_XMMdq_MEMdq | VADDPD_XMMdq_XMMdq_XMMdq | VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VADDPD_YMMqq_YMMqq_MEMqq | VADDPD_YMMqq_YMMqq_YMMqq | VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VADDPS_XMMdq_XMMdq_MEMdq | VADDPS_XMMdq_XMMdq_XMMdq | VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VADDPS_YMMqq_YMMqq_MEMqq | VADDPS_YMMqq_YMMqq_YMMqq | VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VADDSD_XMMdq_XMMdq_MEMq | VADDSD_XMMdq_XMMdq_XMMq | VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VADDSS_XMMdq_XMMdq_MEMd | VADDSS_XMMdq_XMMdq_XMMd | VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VADDSUBPD_XMMdq_XMMdq_MEMdq | VADDSUBPD_XMMdq_XMMdq_XMMdq | VADDSUBPD_YMMqq_YMMqq_MEMqq | VADDSUBPD_YMMqq_YMMqq_YMMqq | VADDSUBPS_XMMdq_XMMdq_MEMdq | VADDSUBPS_XMMdq_XMMdq_XMMdq | VADDSUBPS_YMMqq_YMMqq_MEMqq | VADDSUBPS_YMMqq_YMMqq_YMMqq | VAESDEC_XMMdq_XMMdq_MEMdq | VAESDEC_XMMdq_XMMdq_XMMdq | VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 | VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 | VAESDEC_YMMu128_YMMu128_MEMu128 | VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 | VAESDEC_YMMu128_YMMu128_YMMu128 | VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 | VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 | VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 | VAESDECLAST_XMMdq_XMMdq_MEMdq | VAESDECLAST_XMMdq_XMMdq_XMMdq | VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 | VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 | VAESDECLAST_YMMu128_YMMu128_MEMu128 | VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 | VAESDECLAST_YMMu128_YMMu128_YMMu128 | VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 | VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 | VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 | VAESENC_XMMdq_XMMdq_MEMdq | VAESENC_XMMdq_XMMdq_XMMdq | VAESENC_XMMu128_XMMu128_MEMu128_AVX512 | VAESENC_XMMu128_XMMu128_XMMu128_AVX512 | VAESENC_YMMu128_YMMu128_MEMu128 | VAESENC_YMMu128_YMMu128_MEMu128_AVX512 | VAESENC_YMMu128_YMMu128_YMMu128 | VAESENC_YMMu128_YMMu128_YMMu128_AVX512 | VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 | VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 | VAESENCLAST_XMMdq_XMMdq_MEMdq | VAESENCLAST_XMMdq_XMMdq_XMMdq | VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 | VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 | VAESENCLAST_YMMu128_YMMu128_MEMu128 | VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 | VAESENCLAST_YMMu128_YMMu128_YMMu128 | VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 | VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 | VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 | VAESIMC_XMMdq_MEMdq | VAESIMC_XMMdq_XMMdq | VAESKEYGENASSIST_XMMdq_MEMdq_IMMb | VAESKEYGENASSIST_XMMdq_XMMdq_IMMb | VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 | VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 | VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 | VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 | VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 | VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 | VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 | VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 | VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 | VANDNPD_XMMdq_XMMdq_MEMdq | VANDNPD_XMMdq_XMMdq_XMMdq | VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VANDNPD_YMMqq_YMMqq_MEMqq | VANDNPD_YMMqq_YMMqq_YMMqq | VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VANDNPS_XMMdq_XMMdq_MEMdq | VANDNPS_XMMdq_XMMdq_XMMdq | VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VANDNPS_YMMqq_YMMqq_MEMqq | VANDNPS_YMMqq_YMMqq_YMMqq | VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VANDPD_XMMdq_XMMdq_MEMdq | VANDPD_XMMdq_XMMdq_XMMdq | VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VANDPD_YMMqq_YMMqq_MEMqq | VANDPD_YMMqq_YMMqq_YMMqq | VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VANDPS_XMMdq_XMMdq_MEMdq | VANDPS_XMMdq_XMMdq_XMMdq | VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VANDPS_YMMqq_YMMqq_MEMqq | VANDPS_YMMqq_YMMqq_YMMqq | VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VBCSTNEBF162PS_XMMf32_MEMbf16 | VBCSTNEBF162PS_YMMf32_MEMbf16 | VBCSTNESH2PS_XMMf32_MEMf16 | VBCSTNESH2PS_YMMf32_MEMf16 | VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb | VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb | VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb | VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb | VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb | VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb | VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb | VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb | VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq | VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq | VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq | VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq | VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq | VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq | VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq | VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq | VBROADCASTF128_YMMqq_MEMdq | VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 | VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 | VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 | VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 | VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 | VBROADCASTI128_YMMqq_MEMdq | VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 | VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 | VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 | VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 | VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 | VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 | VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 | VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 | VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 | VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 | VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 | VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 | VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 | VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 | VBROADCASTSD_YMMqq_MEMq | VBROADCASTSD_YMMqq_XMMdq | VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 | VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 | VBROADCASTSS_XMMdq_MEMd | VBROADCASTSS_XMMdq_XMMdq | VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 | VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 | VBROADCASTSS_YMMqq_MEMd | VBROADCASTSS_YMMqq_XMMdq | VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 | VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 | VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 | VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 | VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 | VCMPPD_XMMdq_XMMdq_MEMdq_IMMb | VCMPPD_XMMdq_XMMdq_XMMdq_IMMb | VCMPPD_YMMqq_YMMqq_MEMqq_IMMb | VCMPPD_YMMqq_YMMqq_YMMqq_IMMb | VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 | VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 | VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 | VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 | VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 | VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 | VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 | VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 | VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 | VCMPPS_XMMdq_XMMdq_MEMdq_IMMb | VCMPPS_XMMdq_XMMdq_XMMdq_IMMb | VCMPPS_YMMqq_YMMqq_MEMqq_IMMb | VCMPPS_YMMqq_YMMqq_YMMqq_IMMb | VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VCMPSD_XMMdq_XMMdq_MEMq_IMMb | VCMPSD_XMMdq_XMMdq_XMMq_IMMb | VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 | VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 | VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VCMPSS_XMMdq_XMMdq_MEMd_IMMb | VCMPSS_XMMdq_XMMdq_XMMd_IMMb | VCOMISD_XMMf64_MEMf64_AVX512 | VCOMISD_XMMf64_XMMf64_AVX512 | VCOMISD_XMMq_MEMq | VCOMISD_XMMq_XMMq | VCOMISH_XMMf16_MEMf16_AVX512 | VCOMISH_XMMf16_XMMf16_AVX512 | VCOMISS_XMMd_MEMd | VCOMISS_XMMd_XMMd | VCOMISS_XMMf32_MEMf32_AVX512 | VCOMISS_XMMf32_XMMf32_AVX512 | VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 | VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 | VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 | VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 | VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 | VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 | VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 | VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 | VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 | VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 | VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VCVTDQ2PD_XMMdq_MEMq | VCVTDQ2PD_XMMdq_XMMq | VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 | VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 | VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 | VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 | VCVTDQ2PD_YMMqq_MEMdq | VCVTDQ2PD_YMMqq_XMMdq | VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 | VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 | VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 | VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 | VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 | VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 | VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 | VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 | VCVTDQ2PS_XMMdq_MEMdq | VCVTDQ2PS_XMMdq_XMMdq | VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 | VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 | VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 | VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 | VCVTDQ2PS_YMMqq_MEMqq | VCVTDQ2PS_YMMqq_YMMqq | VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 | VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 | VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 | VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 | VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 | VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 | VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 | VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 | VCVTNEEBF162PS_XMMf32_MEM2bf16 | VCVTNEEBF162PS_YMMf32_MEM2bf16 | VCVTNEEPH2PS_XMMf32_MEM2f16 | VCVTNEEPH2PS_YMMf32_MEM2f16 | VCVTNEOBF162PS_XMMf32_MEM2bf16 | VCVTNEOBF162PS_YMMf32_MEM2bf16 | VCVTNEOPH2PS_XMMf32_MEM2f16 | VCVTNEOPH2PS_YMMf32_MEM2f16 | VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 | VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 | VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 | VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 | VCVTNEPS2BF16_XMMbf16_MEMf32_VL128 | VCVTNEPS2BF16_XMMbf16_MEMf32_VL256 | VCVTNEPS2BF16_XMMbf16_XMMf32 | VCVTNEPS2BF16_XMMbf16_YMMf32 | VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 | VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 | VCVTPD2DQ_XMMdq_MEMdq | VCVTPD2DQ_XMMdq_MEMqq | VCVTPD2DQ_XMMdq_XMMdq | VCVTPD2DQ_XMMdq_YMMqq | VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 | VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 | VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 | VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 | VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 | VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 | VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 | VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 | VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 | VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 | VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 | VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 | VCVTPD2PS_XMMdq_MEMdq | VCVTPD2PS_XMMdq_MEMqq | VCVTPD2PS_XMMdq_XMMdq | VCVTPD2PS_XMMdq_YMMqq | VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 | VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 | VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 | VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 | VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 | VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 | VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 | VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 | VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 | VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 | VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 | VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 | VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 | VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 | VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 | VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 | VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 | VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 | VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 | VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 | VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 | VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 | VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 | VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 | VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 | VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 | VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 | VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 | VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 | VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 | VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 | VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 | VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 | VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 | VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 | VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 | VCVTPH2PS_XMMdq_MEMq | VCVTPH2PS_XMMdq_XMMq | VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 | VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 | VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 | VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 | VCVTPH2PS_YMMqq_MEMdq | VCVTPH2PS_YMMqq_XMMdq | VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 | VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 | VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 | VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 | VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 | VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 | VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 | VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 | VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 | VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 | VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 | VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 | VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 | VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 | VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 | VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 | VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 | VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 | VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 | VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 | VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 | VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 | VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 | VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 | VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 | VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 | VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 | VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 | VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 | VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 | VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 | VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 | VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 | VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 | VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 | VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 | VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 | VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 | VCVTPS2DQ_XMMdq_MEMdq | VCVTPS2DQ_XMMdq_XMMdq | VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 | VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 | VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 | VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 | VCVTPS2DQ_YMMqq_MEMqq | VCVTPS2DQ_YMMqq_YMMqq | VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 | VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 | VCVTPS2PD_XMMdq_MEMq | VCVTPS2PD_XMMdq_XMMq | VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 | VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 | VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 | VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 | VCVTPS2PD_YMMqq_MEMdq | VCVTPS2PD_YMMqq_XMMdq | VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 | VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 | VCVTPS2PH_MEMdq_YMMqq_IMMb | VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 | VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 | VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 | VCVTPS2PH_MEMq_XMMdq_IMMb | VCVTPS2PH_XMMdq_YMMqq_IMMb | VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 | VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 | VCVTPS2PH_XMMq_XMMdq_IMMb | VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 | VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 | VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 | VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 | VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 | VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 | VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 | VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 | VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 | VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 | VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 | VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 | VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 | VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 | VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 | VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 | VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 | VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 | VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 | VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 | VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 | VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 | VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 | VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 | VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 | VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 | VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 | VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 | VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 | VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 | VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 | VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 | VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 | VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 | VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 | VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 | VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 | VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 | VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 | VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 | VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 | VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 | VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 | VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 | VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 | VCVTSD2SI_GPR32d_MEMq | VCVTSD2SI_GPR32d_XMMq | VCVTSD2SI_GPR32i32_MEMf64_AVX512 | VCVTSD2SI_GPR32i32_XMMf64_AVX512 | VCVTSD2SI_GPR64i64_MEMf64_AVX512 | VCVTSD2SI_GPR64i64_XMMf64_AVX512 | VCVTSD2SI_GPR64q_MEMq | VCVTSD2SI_GPR64q_XMMq | VCVTSD2SS_XMMdq_XMMdq_MEMq | VCVTSD2SS_XMMdq_XMMdq_XMMq | VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 | VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 | VCVTSD2USI_GPR32u32_MEMf64_AVX512 | VCVTSD2USI_GPR32u32_XMMf64_AVX512 | VCVTSD2USI_GPR64u64_MEMf64_AVX512 | VCVTSD2USI_GPR64u64_XMMf64_AVX512 | VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 | VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 | VCVTSH2SI_GPR32i32_MEMf16_AVX512 | VCVTSH2SI_GPR32i32_XMMf16_AVX512 | VCVTSH2SI_GPR64i64_MEMf16_AVX512 | VCVTSH2SI_GPR64i64_XMMf16_AVX512 | VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 | VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 | VCVTSH2USI_GPR32u32_MEMf16_AVX512 | VCVTSH2USI_GPR32u32_XMMf16_AVX512 | VCVTSH2USI_GPR64u64_MEMf16_AVX512 | VCVTSH2USI_GPR64u64_XMMf16_AVX512 | VCVTSI2SD_XMMdq_XMMdq_GPR32d | VCVTSI2SD_XMMdq_XMMdq_GPR64q | VCVTSI2SD_XMMdq_XMMdq_MEMd | VCVTSI2SD_XMMdq_XMMdq_MEMq | VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 | VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 | VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 | VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 | VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 | VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 | VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 | VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 | VCVTSI2SS_XMMdq_XMMdq_GPR32d | VCVTSI2SS_XMMdq_XMMdq_GPR64q | VCVTSI2SS_XMMdq_XMMdq_MEMd | VCVTSI2SS_XMMdq_XMMdq_MEMq | VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 | VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 | VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 | VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 | VCVTSS2SD_XMMdq_XMMdq_MEMd | VCVTSS2SD_XMMdq_XMMdq_XMMd | VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 | VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 | VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 | VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 | VCVTSS2SI_GPR32d_MEMd | VCVTSS2SI_GPR32d_XMMd | VCVTSS2SI_GPR32i32_MEMf32_AVX512 | VCVTSS2SI_GPR32i32_XMMf32_AVX512 | VCVTSS2SI_GPR64i64_MEMf32_AVX512 | VCVTSS2SI_GPR64i64_XMMf32_AVX512 | VCVTSS2SI_GPR64q_MEMd | VCVTSS2SI_GPR64q_XMMd | VCVTSS2USI_GPR32u32_MEMf32_AVX512 | VCVTSS2USI_GPR32u32_XMMf32_AVX512 | VCVTSS2USI_GPR64u64_MEMf32_AVX512 | VCVTSS2USI_GPR64u64_XMMf32_AVX512 | VCVTTPD2DQ_XMMdq_MEMdq | VCVTTPD2DQ_XMMdq_MEMqq | VCVTTPD2DQ_XMMdq_XMMdq | VCVTTPD2DQ_XMMdq_YMMqq | VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 | VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 | VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 | VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 | VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 | VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 | VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 | VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 | VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 | VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 | VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 | VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 | VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 | VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 | VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 | VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 | VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 | VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 | VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 | VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 | VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 | VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 | VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 | VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 | VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 | VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 | VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 | VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 | VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 | VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 | VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 | VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 | VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 | VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 | VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 | VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 | VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 | VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 | VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 | VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 | VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 | VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 | VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 | VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 | VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 | VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 | VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 | VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 | VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 | VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 | VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 | VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 | VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 | VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 | VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 | VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 | VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 | VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 | VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 | VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 | VCVTTPS2DQ_XMMdq_MEMdq | VCVTTPS2DQ_XMMdq_XMMdq | VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 | VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 | VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 | VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 | VCVTTPS2DQ_YMMqq_MEMqq | VCVTTPS2DQ_YMMqq_YMMqq | VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 | VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 | VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 | VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 | VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 | VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 | VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 | VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 | VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 | VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 | VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 | VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 | VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 | VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 | VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 | VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 | VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 | VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 | VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 | VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 | VCVTTSD2SI_GPR32d_MEMq | VCVTTSD2SI_GPR32d_XMMq | VCVTTSD2SI_GPR32i32_MEMf64_AVX512 | VCVTTSD2SI_GPR32i32_XMMf64_AVX512 | VCVTTSD2SI_GPR64i64_MEMf64_AVX512 | VCVTTSD2SI_GPR64i64_XMMf64_AVX512 | VCVTTSD2SI_GPR64q_MEMq | VCVTTSD2SI_GPR64q_XMMq | VCVTTSD2USI_GPR32u32_MEMf64_AVX512 | VCVTTSD2USI_GPR32u32_XMMf64_AVX512 | VCVTTSD2USI_GPR64u64_MEMf64_AVX512 | VCVTTSD2USI_GPR64u64_XMMf64_AVX512 | VCVTTSH2SI_GPR32i32_MEMf16_AVX512 | VCVTTSH2SI_GPR32i32_XMMf16_AVX512 | VCVTTSH2SI_GPR64i64_MEMf16_AVX512 | VCVTTSH2SI_GPR64i64_XMMf16_AVX512 | VCVTTSH2USI_GPR32u32_MEMf16_AVX512 | VCVTTSH2USI_GPR32u32_XMMf16_AVX512 | VCVTTSH2USI_GPR64u64_MEMf16_AVX512 | VCVTTSH2USI_GPR64u64_XMMf16_AVX512 | VCVTTSS2SI_GPR32d_MEMd | VCVTTSS2SI_GPR32d_XMMd | VCVTTSS2SI_GPR32i32_MEMf32_AVX512 | VCVTTSS2SI_GPR32i32_XMMf32_AVX512 | VCVTTSS2SI_GPR64i64_MEMf32_AVX512 | VCVTTSS2SI_GPR64i64_XMMf32_AVX512 | VCVTTSS2SI_GPR64q_MEMd | VCVTTSS2SI_GPR64q_XMMd | VCVTTSS2USI_GPR32u32_MEMf32_AVX512 | VCVTTSS2USI_GPR32u32_XMMf32_AVX512 | VCVTTSS2USI_GPR64u64_MEMf32_AVX512 | VCVTTSS2USI_GPR64u64_XMMf32_AVX512 | VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 | VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 | VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 | VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 | VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 | VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 | VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 | VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 | VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 | VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 | VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 | VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 | VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 | VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 | VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 | VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 | VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 | VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 | VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 | VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 | VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 | VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 | VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 | VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 | VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 | VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 | VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 | VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 | VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 | VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 | VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 | VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 | VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 | VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 | VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 | VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 | VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 | VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 | VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 | VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 | VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 | VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 | VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 | VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 | VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 | VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 | VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 | VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 | VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 | VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 | VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 | VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 | VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 | VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 | VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 | VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 | VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 | VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 | VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 | VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 | VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 | VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 | VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 | VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 | VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 | VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 | VDIVPD_XMMdq_XMMdq_MEMdq | VDIVPD_XMMdq_XMMdq_XMMdq | VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VDIVPD_YMMqq_YMMqq_MEMqq | VDIVPD_YMMqq_YMMqq_YMMqq | VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VDIVPS_XMMdq_XMMdq_MEMdq | VDIVPS_XMMdq_XMMdq_XMMdq | VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VDIVPS_YMMqq_YMMqq_MEMqq | VDIVPS_YMMqq_YMMqq_YMMqq | VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VDIVSD_XMMdq_XMMdq_MEMq | VDIVSD_XMMdq_XMMdq_XMMq | VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VDIVSS_XMMdq_XMMdq_MEMd | VDIVSS_XMMdq_XMMdq_XMMd | VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 | VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 | VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 | VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 | VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 | VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VDPPD_XMMdq_XMMdq_MEMdq_IMMb | VDPPD_XMMdq_XMMdq_XMMdq_IMMb | VDPPS_XMMdq_XMMdq_MEMdq_IMMb | VDPPS_XMMdq_XMMdq_XMMdq_IMMb | VDPPS_YMMqq_YMMqq_MEMqq_IMMb | VDPPS_YMMqq_YMMqq_YMMqq_IMMb | VERR_GPR16 | VERR_MEMw | VERW_GPR16 | VERW_MEMw | VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER | VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER | VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER | VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER | VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 | VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 | VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 | VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 | VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 | VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 | VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 | VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 | VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 | VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 | VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VEXTRACTF128_MEMdq_YMMdq_IMMb | VEXTRACTF128_XMMdq_YMMdq_IMMb | VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 | VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 | VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 | VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 | VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VEXTRACTI128_MEMdq_YMMqq_IMMb | VEXTRACTI128_XMMdq_YMMqq_IMMb | VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 | VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 | VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 | VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 | VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VEXTRACTPS_GPR32_XMMdq_IMMb | VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 | VEXTRACTPS_MEMd_XMMdq_IMMb | VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 | VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 | VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 | VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 | VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 | VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 | VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 | VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 | VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 | VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 | VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 | VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 | VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 | VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 | VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 | VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VFMADD132PD_XMMdq_XMMdq_MEMdq | VFMADD132PD_XMMdq_XMMdq_XMMdq | VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMADD132PD_YMMqq_YMMqq_MEMqq | VFMADD132PD_YMMqq_YMMqq_YMMqq | VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMADD132PS_XMMdq_XMMdq_MEMdq | VFMADD132PS_XMMdq_XMMdq_XMMdq | VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMADD132PS_YMMqq_YMMqq_MEMqq | VFMADD132PS_YMMqq_YMMqq_YMMqq | VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMADD132SD_XMMdq_XMMq_MEMq | VFMADD132SD_XMMdq_XMMq_XMMq | VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADD132SS_XMMdq_XMMd_MEMd | VFMADD132SS_XMMdq_XMMd_XMMd | VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADD213PD_XMMdq_XMMdq_MEMdq | VFMADD213PD_XMMdq_XMMdq_XMMdq | VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMADD213PD_YMMqq_YMMqq_MEMqq | VFMADD213PD_YMMqq_YMMqq_YMMqq | VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMADD213PS_XMMdq_XMMdq_MEMdq | VFMADD213PS_XMMdq_XMMdq_XMMdq | VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMADD213PS_YMMqq_YMMqq_MEMqq | VFMADD213PS_YMMqq_YMMqq_YMMqq | VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMADD213SD_XMMdq_XMMq_MEMq | VFMADD213SD_XMMdq_XMMq_XMMq | VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADD213SS_XMMdq_XMMd_MEMd | VFMADD213SS_XMMdq_XMMd_XMMd | VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADD231PD_XMMdq_XMMdq_MEMdq | VFMADD231PD_XMMdq_XMMdq_XMMdq | VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMADD231PD_YMMqq_YMMqq_MEMqq | VFMADD231PD_YMMqq_YMMqq_YMMqq | VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMADD231PS_XMMdq_XMMdq_MEMdq | VFMADD231PS_XMMdq_XMMdq_XMMdq | VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMADD231PS_YMMqq_YMMqq_MEMqq | VFMADD231PS_YMMqq_YMMqq_YMMqq | VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMADD231SD_XMMdq_XMMq_MEMq | VFMADD231SD_XMMdq_XMMq_XMMq | VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADD231SS_XMMdq_XMMd_MEMd | VFMADD231SS_XMMdq_XMMd_XMMd | VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 | VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 | VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 | VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 | VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq | VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq | VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq | VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq | VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq | VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq | VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq | VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq | VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq | VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq | VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq | VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq | VFMADDSD_XMMdq_XMMq_MEMq_XMMq | VFMADDSD_XMMdq_XMMq_XMMq_MEMq | VFMADDSD_XMMdq_XMMq_XMMq_XMMq | VFMADDSS_XMMdq_XMMd_MEMd_XMMd | VFMADDSS_XMMdq_XMMd_XMMd_MEMd | VFMADDSS_XMMdq_XMMd_XMMd_XMMd | VFMADDSUB132PD_XMMdq_XMMdq_MEMdq | VFMADDSUB132PD_XMMdq_XMMdq_XMMdq | VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMADDSUB132PD_YMMqq_YMMqq_MEMqq | VFMADDSUB132PD_YMMqq_YMMqq_YMMqq | VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMADDSUB132PS_XMMdq_XMMdq_MEMdq | VFMADDSUB132PS_XMMdq_XMMdq_XMMdq | VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMADDSUB132PS_YMMqq_YMMqq_MEMqq | VFMADDSUB132PS_YMMqq_YMMqq_YMMqq | VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMADDSUB213PD_XMMdq_XMMdq_MEMdq | VFMADDSUB213PD_XMMdq_XMMdq_XMMdq | VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMADDSUB213PD_YMMqq_YMMqq_MEMqq | VFMADDSUB213PD_YMMqq_YMMqq_YMMqq | VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMADDSUB213PS_XMMdq_XMMdq_MEMdq | VFMADDSUB213PS_XMMdq_XMMdq_XMMdq | VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMADDSUB213PS_YMMqq_YMMqq_MEMqq | VFMADDSUB213PS_YMMqq_YMMqq_YMMqq | VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMADDSUB231PD_XMMdq_XMMdq_MEMdq | VFMADDSUB231PD_XMMdq_XMMdq_XMMdq | VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMADDSUB231PD_YMMqq_YMMqq_MEMqq | VFMADDSUB231PD_YMMqq_YMMqq_YMMqq | VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMADDSUB231PS_XMMdq_XMMdq_MEMdq | VFMADDSUB231PS_XMMdq_XMMdq_XMMdq | VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMADDSUB231PS_YMMqq_YMMqq_MEMqq | VFMADDSUB231PS_YMMqq_YMMqq_YMMqq | VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq | VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq | VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq | VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq | VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq | VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq | VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq | VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq | VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq | VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq | VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq | VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq | VFMSUB132PD_XMMdq_XMMdq_MEMdq | VFMSUB132PD_XMMdq_XMMdq_XMMdq | VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMSUB132PD_YMMqq_YMMqq_MEMqq | VFMSUB132PD_YMMqq_YMMqq_YMMqq | VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMSUB132PS_XMMdq_XMMdq_MEMdq | VFMSUB132PS_XMMdq_XMMdq_XMMdq | VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMSUB132PS_YMMqq_YMMqq_MEMqq | VFMSUB132PS_YMMqq_YMMqq_YMMqq | VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMSUB132SD_XMMdq_XMMq_MEMq | VFMSUB132SD_XMMdq_XMMq_XMMq | VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUB132SS_XMMdq_XMMd_MEMd | VFMSUB132SS_XMMdq_XMMd_XMMd | VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUB213PD_XMMdq_XMMdq_MEMdq | VFMSUB213PD_XMMdq_XMMdq_XMMdq | VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMSUB213PD_YMMqq_YMMqq_MEMqq | VFMSUB213PD_YMMqq_YMMqq_YMMqq | VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMSUB213PS_XMMdq_XMMdq_MEMdq | VFMSUB213PS_XMMdq_XMMdq_XMMdq | VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMSUB213PS_YMMqq_YMMqq_MEMqq | VFMSUB213PS_YMMqq_YMMqq_YMMqq | VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMSUB213SD_XMMdq_XMMq_MEMq | VFMSUB213SD_XMMdq_XMMq_XMMq | VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUB213SS_XMMdq_XMMd_MEMd | VFMSUB213SS_XMMdq_XMMd_XMMd | VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUB231PD_XMMdq_XMMdq_MEMdq | VFMSUB231PD_XMMdq_XMMdq_XMMdq | VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMSUB231PD_YMMqq_YMMqq_MEMqq | VFMSUB231PD_YMMqq_YMMqq_YMMqq | VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMSUB231PS_XMMdq_XMMdq_MEMdq | VFMSUB231PS_XMMdq_XMMdq_XMMdq | VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMSUB231PS_YMMqq_YMMqq_MEMqq | VFMSUB231PS_YMMqq_YMMqq_YMMqq | VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMSUB231SD_XMMdq_XMMq_MEMq | VFMSUB231SD_XMMdq_XMMq_XMMq | VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUB231SS_XMMdq_XMMd_MEMd | VFMSUB231SS_XMMdq_XMMd_XMMd | VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUBADD132PD_XMMdq_XMMdq_MEMdq | VFMSUBADD132PD_XMMdq_XMMdq_XMMdq | VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMSUBADD132PD_YMMqq_YMMqq_MEMqq | VFMSUBADD132PD_YMMqq_YMMqq_YMMqq | VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMSUBADD132PS_XMMdq_XMMdq_MEMdq | VFMSUBADD132PS_XMMdq_XMMdq_XMMdq | VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMSUBADD132PS_YMMqq_YMMqq_MEMqq | VFMSUBADD132PS_YMMqq_YMMqq_YMMqq | VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMSUBADD213PD_XMMdq_XMMdq_MEMdq | VFMSUBADD213PD_XMMdq_XMMdq_XMMdq | VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMSUBADD213PD_YMMqq_YMMqq_MEMqq | VFMSUBADD213PD_YMMqq_YMMqq_YMMqq | VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMSUBADD213PS_XMMdq_XMMdq_MEMdq | VFMSUBADD213PS_XMMdq_XMMdq_XMMdq | VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMSUBADD213PS_YMMqq_YMMqq_MEMqq | VFMSUBADD213PS_YMMqq_YMMqq_YMMqq | VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMSUBADD231PD_XMMdq_XMMdq_MEMdq | VFMSUBADD231PD_XMMdq_XMMdq_XMMdq | VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFMSUBADD231PD_YMMqq_YMMqq_MEMqq | VFMSUBADD231PD_YMMqq_YMMqq_YMMqq | VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFMSUBADD231PS_XMMdq_XMMdq_MEMdq | VFMSUBADD231PS_XMMdq_XMMdq_XMMdq | VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFMSUBADD231PS_YMMqq_YMMqq_MEMqq | VFMSUBADD231PS_YMMqq_YMMqq_YMMqq | VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq | VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq | VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq | VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq | VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq | VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq | VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq | VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq | VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq | VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq | VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq | VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq | VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq | VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq | VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq | VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq | VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq | VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq | VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq | VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq | VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq | VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq | VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq | VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq | VFMSUBSD_XMMdq_XMMq_MEMq_XMMq | VFMSUBSD_XMMdq_XMMq_XMMq_MEMq | VFMSUBSD_XMMdq_XMMq_XMMq_XMMq | VFMSUBSS_XMMdq_XMMd_MEMd_XMMd | VFMSUBSS_XMMdq_XMMd_XMMd_MEMd | VFMSUBSS_XMMdq_XMMd_XMMd_XMMd | VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 | VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 | VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 | VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 | VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 | VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 | VFNMADD132PD_XMMdq_XMMdq_MEMdq | VFNMADD132PD_XMMdq_XMMdq_XMMdq | VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFNMADD132PD_YMMqq_YMMqq_MEMqq | VFNMADD132PD_YMMqq_YMMqq_YMMqq | VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFNMADD132PS_XMMdq_XMMdq_MEMdq | VFNMADD132PS_XMMdq_XMMdq_XMMdq | VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFNMADD132PS_YMMqq_YMMqq_MEMqq | VFNMADD132PS_YMMqq_YMMqq_YMMqq | VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFNMADD132SD_XMMdq_XMMq_MEMq | VFNMADD132SD_XMMdq_XMMq_XMMq | VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMADD132SS_XMMdq_XMMd_MEMd | VFNMADD132SS_XMMdq_XMMd_XMMd | VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMADD213PD_XMMdq_XMMdq_MEMdq | VFNMADD213PD_XMMdq_XMMdq_XMMdq | VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFNMADD213PD_YMMqq_YMMqq_MEMqq | VFNMADD213PD_YMMqq_YMMqq_YMMqq | VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFNMADD213PS_XMMdq_XMMdq_MEMdq | VFNMADD213PS_XMMdq_XMMdq_XMMdq | VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFNMADD213PS_YMMqq_YMMqq_MEMqq | VFNMADD213PS_YMMqq_YMMqq_YMMqq | VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFNMADD213SD_XMMdq_XMMq_MEMq | VFNMADD213SD_XMMdq_XMMq_XMMq | VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMADD213SS_XMMdq_XMMd_MEMd | VFNMADD213SS_XMMdq_XMMd_XMMd | VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMADD231PD_XMMdq_XMMdq_MEMdq | VFNMADD231PD_XMMdq_XMMdq_XMMdq | VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFNMADD231PD_YMMqq_YMMqq_MEMqq | VFNMADD231PD_YMMqq_YMMqq_YMMqq | VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFNMADD231PS_XMMdq_XMMdq_MEMdq | VFNMADD231PS_XMMdq_XMMdq_XMMdq | VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFNMADD231PS_YMMqq_YMMqq_MEMqq | VFNMADD231PS_YMMqq_YMMqq_YMMqq | VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFNMADD231SD_XMMdq_XMMq_MEMq | VFNMADD231SD_XMMdq_XMMq_XMMq | VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMADD231SS_XMMdq_XMMd_MEMd | VFNMADD231SS_XMMdq_XMMd_XMMd | VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq | VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq | VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq | VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq | VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq | VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq | VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq | VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq | VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq | VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq | VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq | VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq | VFNMADDSD_XMMdq_XMMq_MEMq_XMMq | VFNMADDSD_XMMdq_XMMq_XMMq_MEMq | VFNMADDSD_XMMdq_XMMq_XMMq_XMMq | VFNMADDSS_XMMdq_XMMd_MEMd_XMMd | VFNMADDSS_XMMdq_XMMd_XMMd_MEMd | VFNMADDSS_XMMdq_XMMd_XMMd_XMMd | VFNMSUB132PD_XMMdq_XMMdq_MEMdq | VFNMSUB132PD_XMMdq_XMMdq_XMMdq | VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFNMSUB132PD_YMMqq_YMMqq_MEMqq | VFNMSUB132PD_YMMqq_YMMqq_YMMqq | VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFNMSUB132PS_XMMdq_XMMdq_MEMdq | VFNMSUB132PS_XMMdq_XMMdq_XMMdq | VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFNMSUB132PS_YMMqq_YMMqq_MEMqq | VFNMSUB132PS_YMMqq_YMMqq_YMMqq | VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFNMSUB132SD_XMMdq_XMMq_MEMq | VFNMSUB132SD_XMMdq_XMMq_XMMq | VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMSUB132SS_XMMdq_XMMd_MEMd | VFNMSUB132SS_XMMdq_XMMd_XMMd | VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMSUB213PD_XMMdq_XMMdq_MEMdq | VFNMSUB213PD_XMMdq_XMMdq_XMMdq | VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFNMSUB213PD_YMMqq_YMMqq_MEMqq | VFNMSUB213PD_YMMqq_YMMqq_YMMqq | VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFNMSUB213PS_XMMdq_XMMdq_MEMdq | VFNMSUB213PS_XMMdq_XMMdq_XMMdq | VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFNMSUB213PS_YMMqq_YMMqq_MEMqq | VFNMSUB213PS_YMMqq_YMMqq_YMMqq | VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFNMSUB213SD_XMMdq_XMMq_MEMq | VFNMSUB213SD_XMMdq_XMMq_XMMq | VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMSUB213SS_XMMdq_XMMd_MEMd | VFNMSUB213SS_XMMdq_XMMd_XMMd | VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMSUB231PD_XMMdq_XMMdq_MEMdq | VFNMSUB231PD_XMMdq_XMMdq_XMMdq | VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VFNMSUB231PD_YMMqq_YMMqq_MEMqq | VFNMSUB231PD_YMMqq_YMMqq_YMMqq | VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VFNMSUB231PS_XMMdq_XMMdq_MEMdq | VFNMSUB231PS_XMMdq_XMMdq_XMMdq | VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VFNMSUB231PS_YMMqq_YMMqq_MEMqq | VFNMSUB231PS_YMMqq_YMMqq_YMMqq | VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VFNMSUB231SD_XMMdq_XMMq_MEMq | VFNMSUB231SD_XMMdq_XMMq_XMMq | VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VFNMSUB231SS_XMMdq_XMMd_MEMd | VFNMSUB231SS_XMMdq_XMMd_XMMd | VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq | VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq | VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq | VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq | VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq | VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq | VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq | VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq | VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq | VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq | VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq | VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq | VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq | VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq | VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq | VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd | VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd | VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd | VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 | VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 | VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 | VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 | VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 | VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 | VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 | VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 | VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 | VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 | VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 | VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 | VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 | VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 | VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 | VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 | VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 | VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 | VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 | VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 | VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 | VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 | VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 | VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 | VFRCZPD_XMMdq_MEMdq | VFRCZPD_XMMdq_XMMdq | VFRCZPD_YMMqq_MEMqq | VFRCZPD_YMMqq_YMMqq | VFRCZPS_XMMdq_MEMdq | VFRCZPS_XMMdq_XMMdq | VFRCZPS_YMMqq_MEMqq | VFRCZPS_YMMqq_YMMqq | VFRCZSD_XMMdq_MEMq | VFRCZSD_XMMdq_XMMq | VFRCZSS_XMMdq_MEMd | VFRCZSS_XMMdq_XMMd | VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 | VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 | VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 | VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 | VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 | VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 | VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 | VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 | VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 | VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 | VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 | VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 | VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 | VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 | VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 | VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 | VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 | VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 | VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 | VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 | VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 | VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 | VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 | VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 | VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 | VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 | VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 | VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 | VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 | VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 | VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 | VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 | VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 | VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 | VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 | VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 | VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 | VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 | VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 | VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 | VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 | VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 | VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 | VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 | VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 | VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 | VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 | VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 | VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 | VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 | VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 | VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 | VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 | VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 | VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 | VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 | VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 | VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 | VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 | VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 | VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 | VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 | VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 | VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 | VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 | VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 | VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 | VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 | VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 | VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 | VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 | VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 | VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 | VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VGF2P8MULB_XMMu8_XMMu8_MEMu8 | VGF2P8MULB_XMMu8_XMMu8_XMMu8 | VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VGF2P8MULB_YMMu8_YMMu8_MEMu8 | VGF2P8MULB_YMMu8_YMMu8_YMMu8 | VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VHADDPD_XMMdq_XMMdq_MEMdq | VHADDPD_XMMdq_XMMdq_XMMdq | VHADDPD_YMMqq_YMMqq_MEMqq | VHADDPD_YMMqq_YMMqq_YMMqq | VHADDPS_XMMdq_XMMdq_MEMdq | VHADDPS_XMMdq_XMMdq_XMMdq | VHADDPS_YMMqq_YMMqq_MEMqq | VHADDPS_YMMqq_YMMqq_YMMqq | VHSUBPD_XMMdq_XMMdq_MEMdq | VHSUBPD_XMMdq_XMMdq_XMMdq | VHSUBPD_YMMqq_YMMqq_MEMqq | VHSUBPD_YMMqq_YMMqq_YMMqq | VHSUBPS_XMMdq_XMMdq_MEMdq | VHSUBPS_XMMdq_XMMdq_XMMdq | VHSUBPS_YMMqq_YMMqq_MEMqq | VHSUBPS_YMMqq_YMMqq_YMMqq | VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb | VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb | VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 | VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 | VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 | VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 | VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 | VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 | VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 | VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 | VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb | VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb | VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 | VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 | VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 | VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 | VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 | VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 | VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 | VINSERTPS_XMMdq_XMMdq_MEMd_IMMb | VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb | VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 | VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 | VLDDQU_XMMdq_MEMdq | VLDDQU_YMMqq_MEMqq | VLDMXCSR_MEMd | VMASKMOVDQU_XMMxub_XMMxub | VMASKMOVPD_MEMdq_XMMdq_XMMdq | VMASKMOVPD_MEMqq_YMMqq_YMMqq | VMASKMOVPD_XMMdq_XMMdq_MEMdq | VMASKMOVPD_YMMqq_YMMqq_MEMqq | VMASKMOVPS_MEMdq_XMMdq_XMMdq | VMASKMOVPS_MEMqq_YMMqq_YMMqq | VMASKMOVPS_XMMdq_XMMdq_MEMdq | VMASKMOVPS_YMMqq_YMMqq_MEMqq | VMAXPD_XMMdq_XMMdq_MEMdq | VMAXPD_XMMdq_XMMdq_XMMdq | VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VMAXPD_YMMqq_YMMqq_MEMqq | VMAXPD_YMMqq_YMMqq_YMMqq | VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VMAXPS_XMMdq_XMMdq_MEMdq | VMAXPS_XMMdq_XMMdq_XMMdq | VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VMAXPS_YMMqq_YMMqq_MEMqq | VMAXPS_YMMqq_YMMqq_YMMqq | VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VMAXSD_XMMdq_XMMdq_MEMq | VMAXSD_XMMdq_XMMdq_XMMq | VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VMAXSS_XMMdq_XMMdq_MEMd | VMAXSS_XMMdq_XMMdq_XMMd | VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VMCALL | VMCLEAR_MEMq | VMFUNC | VMINPD_XMMdq_XMMdq_MEMdq | VMINPD_XMMdq_XMMdq_XMMdq | VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VMINPD_YMMqq_YMMqq_MEMqq | VMINPD_YMMqq_YMMqq_YMMqq | VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VMINPS_XMMdq_XMMdq_MEMdq | VMINPS_XMMdq_XMMdq_XMMdq | VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VMINPS_YMMqq_YMMqq_MEMqq | VMINPS_YMMqq_YMMqq_YMMqq | VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VMINSD_XMMdq_XMMdq_MEMq | VMINSD_XMMdq_XMMdq_XMMq | VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VMINSS_XMMdq_XMMdq_MEMd | VMINSS_XMMdq_XMMdq_XMMd | VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VMLAUNCH | VMLOAD_ArAX | VMMCALL | VMOVAPD_MEMdq_XMMdq | VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 | VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 | VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 | VMOVAPD_MEMqq_YMMqq | VMOVAPD_XMMdq_MEMdq | VMOVAPD_XMMdq_XMMdq_28 | VMOVAPD_XMMdq_XMMdq_29 | VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 | VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 | VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 | VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 | VMOVAPD_YMMqq_MEMqq | VMOVAPD_YMMqq_YMMqq_28 | VMOVAPD_YMMqq_YMMqq_29 | VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 | VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VMOVAPS_MEMdq_XMMdq | VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 | VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 | VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 | VMOVAPS_MEMqq_YMMqq | VMOVAPS_XMMdq_MEMdq | VMOVAPS_XMMdq_XMMdq_28 | VMOVAPS_XMMdq_XMMdq_29 | VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 | VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 | VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 | VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 | VMOVAPS_YMMqq_MEMqq | VMOVAPS_YMMqq_YMMqq_28 | VMOVAPS_YMMqq_YMMqq_29 | VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 | VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VMOVD_GPR32d_XMMd | VMOVD_GPR32u32_XMMu32_AVX512 | VMOVD_MEMd_XMMd | VMOVD_MEMu32_XMMu32_AVX512 | VMOVD_XMMdq_GPR32d | VMOVD_XMMdq_MEMd | VMOVD_XMMu32_GPR32u32_AVX512 | VMOVD_XMMu32_MEMu32_AVX512 | VMOVDDUP_XMMdq_MEMq | VMOVDDUP_XMMdq_XMMq | VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 | VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 | VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 | VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 | VMOVDDUP_YMMqq_MEMqq | VMOVDDUP_YMMqq_YMMqq | VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 | VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 | VMOVDQA_MEMdq_XMMdq | VMOVDQA_MEMqq_YMMqq | VMOVDQA_XMMdq_MEMdq | VMOVDQA_XMMdq_XMMdq_6F | VMOVDQA_XMMdq_XMMdq_7F | VMOVDQA_YMMqq_MEMqq | VMOVDQA_YMMqq_YMMqq_6F | VMOVDQA_YMMqq_YMMqq_7F | VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 | VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 | VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 | VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 | VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 | VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 | VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 | VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 | VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 | VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 | VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 | VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 | VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 | VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 | VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 | VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 | VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 | VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 | VMOVDQU_MEMdq_XMMdq | VMOVDQU_MEMqq_YMMqq | VMOVDQU_XMMdq_MEMdq | VMOVDQU_XMMdq_XMMdq_6F | VMOVDQU_XMMdq_XMMdq_7F | VMOVDQU_YMMqq_MEMqq | VMOVDQU_YMMqq_YMMqq_6F | VMOVDQU_YMMqq_YMMqq_7F | VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 | VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 | VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 | VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 | VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 | VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 | VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 | VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 | VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 | VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 | VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 | VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 | VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 | VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 | VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 | VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 | VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 | VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 | VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 | VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 | VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 | VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 | VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 | VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 | VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 | VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 | VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 | VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 | VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 | VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 | VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 | VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 | VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 | VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 | VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 | VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 | VMOVHLPS_XMMdq_XMMdq_XMMdq | VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 | VMOVHPD_MEMf64_XMMf64_AVX512 | VMOVHPD_MEMq_XMMdq | VMOVHPD_XMMdq_XMMq_MEMq | VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 | VMOVHPS_MEMf32_XMMf32_AVX512 | VMOVHPS_MEMq_XMMdq | VMOVHPS_XMMdq_XMMq_MEMq | VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 | VMOVLHPS_XMMdq_XMMq_XMMq | VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 | VMOVLPD_MEMf64_XMMf64_AVX512 | VMOVLPD_MEMq_XMMq | VMOVLPD_XMMdq_XMMdq_MEMq | VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 | VMOVLPS_MEMf32_XMMf32_AVX512 | VMOVLPS_MEMq_XMMq | VMOVLPS_XMMdq_XMMdq_MEMq | VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 | VMOVMSKPD_GPR32d_XMMdq | VMOVMSKPD_GPR32d_YMMqq | VMOVMSKPS_GPR32d_XMMdq | VMOVMSKPS_GPR32d_YMMqq | VMOVNTDQ_MEMdq_XMMdq | VMOVNTDQ_MEMqq_YMMqq | VMOVNTDQ_MEMu32_XMMu32_AVX512 | VMOVNTDQ_MEMu32_YMMu32_AVX512 | VMOVNTDQ_MEMu32_ZMMu32_AVX512 | VMOVNTDQA_XMMdq_MEMdq | VMOVNTDQA_XMMu32_MEMu32_AVX512 | VMOVNTDQA_YMMqq_MEMqq | VMOVNTDQA_YMMu32_MEMu32_AVX512 | VMOVNTDQA_ZMMu32_MEMu32_AVX512 | VMOVNTPD_MEMdq_XMMdq | VMOVNTPD_MEMf64_XMMf64_AVX512 | VMOVNTPD_MEMf64_YMMf64_AVX512 | VMOVNTPD_MEMf64_ZMMf64_AVX512 | VMOVNTPD_MEMqq_YMMqq | VMOVNTPS_MEMdq_XMMdq | VMOVNTPS_MEMf32_XMMf32_AVX512 | VMOVNTPS_MEMf32_YMMf32_AVX512 | VMOVNTPS_MEMf32_ZMMf32_AVX512 | VMOVNTPS_MEMqq_YMMqq | VMOVQ_GPR64q_XMMq | VMOVQ_GPR64u64_XMMu64_AVX512 | VMOVQ_MEMq_XMMq_7E | VMOVQ_MEMq_XMMq_D6 | VMOVQ_MEMu64_XMMu64_AVX512 | VMOVQ_XMMdq_GPR64q | VMOVQ_XMMdq_MEMq_6E | VMOVQ_XMMdq_MEMq_7E | VMOVQ_XMMdq_XMMq_7E | VMOVQ_XMMdq_XMMq_D6 | VMOVQ_XMMu64_GPR64u64_AVX512 | VMOVQ_XMMu64_MEMu64_AVX512 | VMOVQ_XMMu64_XMMu64_AVX512 | VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 | VMOVSD_MEMq_XMMq | VMOVSD_XMMdq_MEMq | VMOVSD_XMMdq_XMMdq_XMMq_10 | VMOVSD_XMMdq_XMMdq_XMMq_11 | VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 | VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 | VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 | VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VMOVSHDUP_XMMdq_MEMdq | VMOVSHDUP_XMMdq_XMMdq | VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 | VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 | VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 | VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 | VMOVSHDUP_YMMqq_MEMqq | VMOVSHDUP_YMMqq_YMMqq | VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 | VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 | VMOVSLDUP_XMMdq_MEMdq | VMOVSLDUP_XMMdq_XMMdq | VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 | VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 | VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 | VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 | VMOVSLDUP_YMMqq_MEMqq | VMOVSLDUP_YMMqq_YMMqq | VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 | VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 | VMOVSS_MEMd_XMMd | VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 | VMOVSS_XMMdq_MEMd | VMOVSS_XMMdq_XMMdq_XMMd_10 | VMOVSS_XMMdq_XMMdq_XMMd_11 | VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 | VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VMOVUPD_MEMdq_XMMdq | VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 | VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 | VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 | VMOVUPD_MEMqq_YMMqq | VMOVUPD_XMMdq_MEMdq | VMOVUPD_XMMdq_XMMdq_10 | VMOVUPD_XMMdq_XMMdq_11 | VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 | VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 | VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 | VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 | VMOVUPD_YMMqq_MEMqq | VMOVUPD_YMMqq_YMMqq_10 | VMOVUPD_YMMqq_YMMqq_11 | VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 | VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VMOVUPS_MEMdq_XMMdq | VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 | VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 | VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 | VMOVUPS_MEMqq_YMMqq | VMOVUPS_XMMdq_MEMdq | VMOVUPS_XMMdq_XMMdq_10 | VMOVUPS_XMMdq_XMMdq_11 | VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 | VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 | VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 | VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 | VMOVUPS_YMMqq_MEMqq | VMOVUPS_YMMqq_YMMqq_10 | VMOVUPS_YMMqq_YMMqq_11 | VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 | VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VMOVW_GPR32f16_XMMf16_AVX512 | VMOVW_MEMf16_XMMf16_AVX512 | VMOVW_XMMf16_GPR32f16_AVX512 | VMOVW_XMMf16_MEMf16_AVX512 | VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb | VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb | VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb | VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb | VMPTRLD_MEMq | VMPTRST_MEMq | VMREAD_GPR32_GPR32 | VMREAD_GPR64_GPR64 | VMREAD_MEMd_GPR32 | VMREAD_MEMq_GPR64 | VMRESUME | VMRUN_ArAX | VMSAVE | VMULPD_XMMdq_XMMdq_MEMdq | VMULPD_XMMdq_XMMdq_XMMdq | VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VMULPD_YMMqq_YMMqq_MEMqq | VMULPD_YMMqq_YMMqq_YMMqq | VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VMULPS_XMMdq_XMMdq_MEMdq | VMULPS_XMMdq_XMMdq_XMMdq | VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VMULPS_YMMqq_YMMqq_MEMqq | VMULPS_YMMqq_YMMqq_YMMqq | VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VMULSD_XMMdq_XMMdq_MEMq | VMULSD_XMMdq_XMMdq_XMMq | VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VMULSS_XMMdq_XMMdq_MEMd | VMULSS_XMMdq_XMMdq_XMMd | VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VMWRITE_GPR32_GPR32 | VMWRITE_GPR32_MEMd | VMWRITE_GPR64_GPR64 | VMWRITE_GPR64_MEMq | VMXOFF | VMXON_MEMq | VORPD_XMMdq_XMMdq_MEMdq | VORPD_XMMdq_XMMdq_XMMdq | VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VORPD_YMMqq_YMMqq_MEMqq | VORPD_YMMqq_YMMqq_YMMqq | VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VORPS_XMMdq_XMMdq_MEMdq | VORPS_XMMdq_XMMdq_XMMdq | VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VORPS_YMMqq_YMMqq_MEMqq | VORPS_YMMqq_YMMqq_YMMqq | VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 | VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 | VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 | VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 | VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 | VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 | VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 | VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 | VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 | VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 | VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 | VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 | VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 | VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 | VPABSB_XMMdq_MEMdq | VPABSB_XMMdq_XMMdq | VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 | VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 | VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 | VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 | VPABSB_YMMqq_MEMqq | VPABSB_YMMqq_YMMqq | VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 | VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 | VPABSD_XMMdq_MEMdq | VPABSD_XMMdq_XMMdq | VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 | VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 | VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 | VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 | VPABSD_YMMqq_MEMqq | VPABSD_YMMqq_YMMqq | VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 | VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 | VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 | VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 | VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 | VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 | VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 | VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 | VPABSW_XMMdq_MEMdq | VPABSW_XMMdq_XMMdq | VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 | VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 | VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 | VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 | VPABSW_YMMqq_MEMqq | VPABSW_YMMqq_YMMqq | VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 | VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 | VPACKSSDW_XMMdq_XMMdq_MEMdq | VPACKSSDW_XMMdq_XMMdq_XMMdq | VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 | VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 | VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 | VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 | VPACKSSDW_YMMqq_YMMqq_MEMqq | VPACKSSDW_YMMqq_YMMqq_YMMqq | VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 | VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 | VPACKSSWB_XMMdq_XMMdq_MEMdq | VPACKSSWB_XMMdq_XMMdq_XMMdq | VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 | VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 | VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 | VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 | VPACKSSWB_YMMqq_YMMqq_MEMqq | VPACKSSWB_YMMqq_YMMqq_YMMqq | VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 | VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPACKUSDW_XMMdq_XMMdq_MEMdq | VPACKUSDW_XMMdq_XMMdq_XMMdq | VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 | VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 | VPACKUSDW_YMMqq_YMMqq_MEMqq | VPACKUSDW_YMMqq_YMMqq_YMMqq | VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 | VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 | VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 | VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPACKUSWB_XMMdq_XMMdq_MEMdq | VPACKUSWB_XMMdq_XMMdq_XMMdq | VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 | VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 | VPACKUSWB_YMMqq_YMMqq_MEMqq | VPACKUSWB_YMMqq_YMMqq_YMMqq | VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 | VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 | VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 | VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPADDB_XMMdq_XMMdq_MEMdq | VPADDB_XMMdq_XMMdq_XMMdq | VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPADDB_YMMqq_YMMqq_MEMqq | VPADDB_YMMqq_YMMqq_YMMqq | VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPADDD_XMMdq_XMMdq_MEMdq | VPADDD_XMMdq_XMMdq_XMMdq | VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPADDD_YMMqq_YMMqq_MEMqq | VPADDD_YMMqq_YMMqq_YMMqq | VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPADDQ_XMMdq_XMMdq_MEMdq | VPADDQ_XMMdq_XMMdq_XMMdq | VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPADDQ_YMMqq_YMMqq_MEMqq | VPADDQ_YMMqq_YMMqq_YMMqq | VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPADDSB_XMMdq_XMMdq_MEMdq | VPADDSB_XMMdq_XMMdq_XMMdq | VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 | VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 | VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 | VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 | VPADDSB_YMMqq_YMMqq_MEMqq | VPADDSB_YMMqq_YMMqq_YMMqq | VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 | VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 | VPADDSW_XMMdq_XMMdq_MEMdq | VPADDSW_XMMdq_XMMdq_XMMdq | VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 | VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 | VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 | VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 | VPADDSW_YMMqq_YMMqq_MEMqq | VPADDSW_YMMqq_YMMqq_YMMqq | VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 | VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPADDUSB_XMMdq_XMMdq_MEMdq | VPADDUSB_XMMdq_XMMdq_XMMdq | VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPADDUSB_YMMqq_YMMqq_MEMqq | VPADDUSB_YMMqq_YMMqq_YMMqq | VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPADDUSW_XMMdq_XMMdq_MEMdq | VPADDUSW_XMMdq_XMMdq_XMMdq | VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPADDUSW_YMMqq_YMMqq_MEMqq | VPADDUSW_YMMqq_YMMqq_YMMqq | VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPADDW_XMMdq_XMMdq_MEMdq | VPADDW_XMMdq_XMMdq_XMMdq | VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPADDW_YMMqq_YMMqq_MEMqq | VPADDW_YMMqq_YMMqq_YMMqq | VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb | VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb | VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 | VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 | VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb | VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb | VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 | VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 | VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 | VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 | VPAND_XMMdq_XMMdq_MEMdq | VPAND_XMMdq_XMMdq_XMMdq | VPAND_YMMqq_YMMqq_MEMqq | VPAND_YMMqq_YMMqq_YMMqq | VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPANDN_XMMdq_XMMdq_MEMdq | VPANDN_XMMdq_XMMdq_XMMdq | VPANDN_YMMqq_YMMqq_MEMqq | VPANDN_YMMqq_YMMqq_YMMqq | VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPAVGB_XMMdq_XMMdq_MEMdq | VPAVGB_XMMdq_XMMdq_XMMdq | VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPAVGB_YMMqq_YMMqq_MEMqq | VPAVGB_YMMqq_YMMqq_YMMqq | VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPAVGW_XMMdq_XMMdq_MEMdq | VPAVGW_XMMdq_XMMdq_XMMdq | VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPAVGW_YMMqq_YMMqq_MEMqq | VPAVGW_YMMqq_YMMqq_YMMqq | VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb | VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb | VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb | VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb | VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq | VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq | VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq | VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq | VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb | VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb | VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb | VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb | VPBROADCASTB_XMMdq_MEMb | VPBROADCASTB_XMMdq_XMMb | VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 | VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 | VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 | VPBROADCASTB_YMMqq_MEMb | VPBROADCASTB_YMMqq_XMMb | VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 | VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 | VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 | VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 | VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 | VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 | VPBROADCASTD_XMMdq_MEMd | VPBROADCASTD_XMMdq_XMMd | VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 | VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 | VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 | VPBROADCASTD_YMMqq_MEMd | VPBROADCASTD_YMMqq_XMMd | VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 | VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 | VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 | VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 | VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 | VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 | VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 | VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 | VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD | VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 | VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 | VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD | VPBROADCASTQ_XMMdq_MEMq | VPBROADCASTQ_XMMdq_XMMq | VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 | VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 | VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 | VPBROADCASTQ_YMMqq_MEMq | VPBROADCASTQ_YMMqq_XMMq | VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 | VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 | VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 | VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 | VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 | VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 | VPBROADCASTW_XMMdq_MEMw | VPBROADCASTW_XMMdq_XMMw | VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 | VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 | VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 | VPBROADCASTW_YMMqq_MEMw | VPBROADCASTW_YMMqq_XMMw | VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 | VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 | VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 | VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 | VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 | VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 | VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb | VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb | VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 | VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 | VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 | VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 | VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 | VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 | VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 | VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 | VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq | VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq | VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq | VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq | VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq | VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq | VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 | VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 | VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 | VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 | VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 | VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 | VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 | VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 | VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 | VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 | VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 | VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 | VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 | VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 | VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 | VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 | VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 | VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPCMPEQB_XMMdq_XMMdq_MEMdq | VPCMPEQB_XMMdq_XMMdq_XMMdq | VPCMPEQB_YMMqq_YMMqq_MEMqq | VPCMPEQB_YMMqq_YMMqq_YMMqq | VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 | VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 | VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 | VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 | VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 | VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPCMPEQD_XMMdq_XMMdq_MEMdq | VPCMPEQD_XMMdq_XMMdq_XMMdq | VPCMPEQD_YMMqq_YMMqq_MEMqq | VPCMPEQD_YMMqq_YMMqq_YMMqq | VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 | VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 | VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 | VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 | VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 | VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPCMPEQQ_XMMdq_XMMdq_MEMdq | VPCMPEQQ_XMMdq_XMMdq_XMMdq | VPCMPEQQ_YMMqq_YMMqq_MEMqq | VPCMPEQQ_YMMqq_YMMqq_YMMqq | VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 | VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 | VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 | VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 | VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 | VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPCMPEQW_XMMdq_XMMdq_MEMdq | VPCMPEQW_XMMdq_XMMdq_XMMdq | VPCMPEQW_YMMqq_YMMqq_MEMqq | VPCMPEQW_YMMqq_YMMqq_YMMqq | VPCMPESTRI_XMMdq_MEMdq_IMMb | VPCMPESTRI_XMMdq_XMMdq_IMMb | VPCMPESTRI64_XMMdq_MEMdq_IMMb | VPCMPESTRI64_XMMdq_XMMdq_IMMb | VPCMPESTRM_XMMdq_MEMdq_IMMb | VPCMPESTRM_XMMdq_XMMdq_IMMb | VPCMPESTRM64_XMMdq_MEMdq_IMMb | VPCMPESTRM64_XMMdq_XMMdq_IMMb | VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 | VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 | VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 | VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 | VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 | VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPCMPGTB_XMMdq_XMMdq_MEMdq | VPCMPGTB_XMMdq_XMMdq_XMMdq | VPCMPGTB_YMMqq_YMMqq_MEMqq | VPCMPGTB_YMMqq_YMMqq_YMMqq | VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 | VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 | VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 | VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 | VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 | VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 | VPCMPGTD_XMMdq_XMMdq_MEMdq | VPCMPGTD_XMMdq_XMMdq_XMMdq | VPCMPGTD_YMMqq_YMMqq_MEMqq | VPCMPGTD_YMMqq_YMMqq_YMMqq | VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 | VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 | VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 | VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 | VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 | VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 | VPCMPGTQ_XMMdq_XMMdq_MEMdq | VPCMPGTQ_XMMdq_XMMdq_XMMdq | VPCMPGTQ_YMMqq_YMMqq_MEMqq | VPCMPGTQ_YMMqq_YMMqq_YMMqq | VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 | VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 | VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 | VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 | VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 | VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPCMPGTW_XMMdq_XMMdq_MEMdq | VPCMPGTW_XMMdq_XMMdq_XMMdq | VPCMPGTW_YMMqq_YMMqq_MEMqq | VPCMPGTW_YMMqq_YMMqq_YMMqq | VPCMPISTRI_XMMdq_MEMdq_IMMb | VPCMPISTRI_XMMdq_XMMdq_IMMb | VPCMPISTRI64_XMMdq_MEMdq_IMMb | VPCMPISTRI64_XMMdq_XMMdq_IMMb | VPCMPISTRM_XMMdq_MEMdq_IMMb | VPCMPISTRM_XMMdq_XMMdq_IMMb | VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 | VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 | VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 | VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 | VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 | VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 | VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 | VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 | VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 | VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 | VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 | VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 | VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 | VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 | VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 | VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 | VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 | VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 | VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 | VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 | VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 | VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 | VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 | VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 | VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 | VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 | VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 | VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 | VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 | VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 | VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 | VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 | VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 | VPCOMB_XMMdq_XMMdq_MEMdq_IMMb | VPCOMB_XMMdq_XMMdq_XMMdq_IMMb | VPCOMD_XMMdq_XMMdq_MEMdq_IMMb | VPCOMD_XMMdq_XMMdq_XMMdq_IMMb | VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 | VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 | VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 | VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 | VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 | VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 | VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 | VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 | VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 | VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 | VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 | VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 | VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 | VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 | VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 | VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 | VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 | VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 | VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 | VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 | VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 | VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 | VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 | VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 | VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb | VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb | VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb | VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb | VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb | VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb | VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb | VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb | VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb | VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb | VPCOMW_XMMdq_XMMdq_MEMdq_IMMb | VPCOMW_XMMdq_XMMdq_XMMdq_IMMb | VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 | VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 | VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 | VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 | VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD | VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD | VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 | VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 | VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 | VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 | VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD | VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD | VPDPBSSD_XMMi32_XMM4i8_MEM4i8 | VPDPBSSD_XMMi32_XMM4i8_XMM4i8 | VPDPBSSD_YMMi32_YMM4i8_MEM4i8 | VPDPBSSD_YMMi32_YMM4i8_YMM4i8 | VPDPBSSDS_XMMi32_XMM4i8_MEM4i8 | VPDPBSSDS_XMMi32_XMM4i8_XMM4i8 | VPDPBSSDS_YMMi32_YMM4i8_MEM4i8 | VPDPBSSDS_YMMi32_YMM4i8_YMM4i8 | VPDPBSUD_XMMi32_XMM4i8_MEM4u8 | VPDPBSUD_XMMi32_XMM4i8_XMM4u8 | VPDPBSUD_YMMi32_YMM4i8_MEM4u8 | VPDPBSUD_YMMi32_YMM4i8_YMM4u8 | VPDPBSUDS_XMMi32_XMM4i8_MEM4u8 | VPDPBSUDS_XMMi32_XMM4i8_XMM4u8 | VPDPBSUDS_YMMi32_YMM4i8_MEM4u8 | VPDPBSUDS_YMMi32_YMM4i8_YMM4u8 | VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 | VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 | VPDPBUSD_XMMi32_XMMu32_MEMu32 | VPDPBUSD_XMMi32_XMMu32_XMMu32 | VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 | VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 | VPDPBUSD_YMMi32_YMMu32_MEMu32 | VPDPBUSD_YMMi32_YMMu32_YMMu32 | VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 | VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 | VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 | VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 | VPDPBUSDS_XMMi32_XMMu32_MEMu32 | VPDPBUSDS_XMMi32_XMMu32_XMMu32 | VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 | VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 | VPDPBUSDS_YMMi32_YMMu32_MEMu32 | VPDPBUSDS_YMMi32_YMMu32_YMMu32 | VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 | VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 | VPDPBUUD_XMMu32_XMM4u8_MEM4u8 | VPDPBUUD_XMMu32_XMM4u8_XMM4u8 | VPDPBUUD_YMMu32_YMM4u8_MEM4u8 | VPDPBUUD_YMMu32_YMM4u8_YMM4u8 | VPDPBUUDS_XMMu32_XMM4u8_MEM4u8 | VPDPBUUDS_XMMu32_XMM4u8_XMM4u8 | VPDPBUUDS_YMMu32_YMM4u8_MEM4u8 | VPDPBUUDS_YMMu32_YMM4u8_YMM4u8 | VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 | VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 | VPDPWSSD_XMMi32_XMMu32_MEMu32 | VPDPWSSD_XMMi32_XMMu32_XMMu32 | VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 | VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 | VPDPWSSD_YMMi32_YMMu32_MEMu32 | VPDPWSSD_YMMi32_YMMu32_YMMu32 | VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 | VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 | VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 | VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 | VPDPWSSDS_XMMi32_XMMu32_MEMu32 | VPDPWSSDS_XMMi32_XMMu32_XMMu32 | VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 | VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 | VPDPWSSDS_YMMi32_YMMu32_MEMu32 | VPDPWSSDS_YMMi32_YMMu32_YMMu32 | VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 | VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 | VPDPWSUD_XMMi32_XMM2i16_MEM2u16 | VPDPWSUD_XMMi32_XMM2i16_XMM2u16 | VPDPWSUD_YMMi32_YMM2i16_MEM2u16 | VPDPWSUD_YMMi32_YMM2i16_YMM2u16 | VPDPWSUDS_XMMi32_XMM2i16_MEM2u16 | VPDPWSUDS_XMMi32_XMM2i16_XMM2u16 | VPDPWSUDS_YMMi32_YMM2i16_MEM2u16 | VPDPWSUDS_YMMi32_YMM2i16_YMM2u16 | VPDPWUSD_XMMi32_XMM2u16_MEM2i16 | VPDPWUSD_XMMi32_XMM2u16_XMM2i16 | VPDPWUSD_YMMi32_YMM2u16_MEM2i16 | VPDPWUSD_YMMi32_YMM2u16_YMM2i16 | VPDPWUSDS_XMMi32_XMM2u16_MEM2i16 | VPDPWUSDS_XMMi32_XMM2u16_XMM2i16 | VPDPWUSDS_YMMi32_YMM2u16_MEM2i16 | VPDPWUSDS_YMMi32_YMM2u16_YMM2i16 | VPDPWUUD_XMMu32_XMM2u16_MEM2u16 | VPDPWUUD_XMMu32_XMM2u16_XMM2u16 | VPDPWUUD_YMMu32_YMM2u16_MEM2u16 | VPDPWUUD_YMMu32_YMM2u16_YMM2u16 | VPDPWUUDS_XMMu32_XMM2u16_MEM2u16 | VPDPWUUDS_XMMu32_XMM2u16_XMM2u16 | VPDPWUUDS_YMMu32_YMM2u16_MEM2u16 | VPDPWUUDS_YMMu32_YMM2u16_YMM2u16 | VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb | VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb | VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb | VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb | VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPERMD_YMMqq_YMMqq_MEMqq | VPERMD_YMMqq_YMMqq_YMMqq | VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb | VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb | VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb | VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb | VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb | VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb | VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb | VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb | VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb | VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb | VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb | VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb | VPERMILPD_XMMdq_MEMdq_IMMb | VPERMILPD_XMMdq_XMMdq_IMMb | VPERMILPD_XMMdq_XMMdq_MEMdq | VPERMILPD_XMMdq_XMMdq_XMMdq | VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 | VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 | VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VPERMILPD_YMMqq_MEMqq_IMMb | VPERMILPD_YMMqq_YMMqq_IMMb | VPERMILPD_YMMqq_YMMqq_MEMqq | VPERMILPD_YMMqq_YMMqq_YMMqq | VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VPERMILPS_XMMdq_MEMdq_IMMb | VPERMILPS_XMMdq_XMMdq_IMMb | VPERMILPS_XMMdq_XMMdq_MEMdq | VPERMILPS_XMMdq_XMMdq_XMMdq | VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 | VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 | VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VPERMILPS_YMMqq_MEMqq_IMMb | VPERMILPS_YMMqq_YMMqq_IMMb | VPERMILPS_YMMqq_YMMqq_MEMqq | VPERMILPS_YMMqq_YMMqq_YMMqq | VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 | VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VPERMPD_YMMqq_MEMqq_IMMb | VPERMPD_YMMqq_YMMqq_IMMb | VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VPERMPS_YMMqq_YMMqq_MEMqq | VPERMPS_YMMqq_YMMqq_YMMqq | VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VPERMQ_YMMqq_MEMqq_IMMb | VPERMQ_YMMqq_YMMqq_IMMb | VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 | VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 | VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 | VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 | VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 | VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 | VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 | VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 | VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 | VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 | VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 | VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 | VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 | VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 | VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 | VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 | VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 | VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 | VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 | VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 | VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 | VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 | VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 | VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 | VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 | VPEXTRB_GPR32d_XMMdq_IMMb | VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 | VPEXTRB_MEMb_XMMdq_IMMb | VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 | VPEXTRD_GPR32d_XMMdq_IMMb | VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 | VPEXTRD_MEMd_XMMdq_IMMb | VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 | VPEXTRQ_GPR64q_XMMdq_IMMb | VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 | VPEXTRQ_MEMq_XMMdq_IMMb | VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 | VPEXTRW_GPR32d_XMMdq_IMMb_15 | VPEXTRW_GPR32d_XMMdq_IMMb_C5 | VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 | VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 | VPEXTRW_MEMw_XMMdq_IMMb | VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 | VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 | VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 | VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 | VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 | VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 | VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 | VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 | VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 | VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 | VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 | VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 | VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 | VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 | VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 | VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 | VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 | VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 | VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 | VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 | VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 | VPHADDBD_XMMdq_MEMdq | VPHADDBD_XMMdq_XMMdq | VPHADDBQ_XMMdq_MEMdq | VPHADDBQ_XMMdq_XMMdq | VPHADDBW_XMMdq_MEMdq | VPHADDBW_XMMdq_XMMdq | VPHADDD_XMMdq_XMMdq_MEMdq | VPHADDD_XMMdq_XMMdq_XMMdq | VPHADDD_YMMqq_YMMqq_MEMqq | VPHADDD_YMMqq_YMMqq_YMMqq | VPHADDDQ_XMMdq_MEMdq | VPHADDDQ_XMMdq_XMMdq | VPHADDSW_XMMdq_XMMdq_MEMdq | VPHADDSW_XMMdq_XMMdq_XMMdq | VPHADDSW_YMMqq_YMMqq_MEMqq | VPHADDSW_YMMqq_YMMqq_YMMqq | VPHADDUBD_XMMdq_MEMdq | VPHADDUBD_XMMdq_XMMdq | VPHADDUBQ_XMMdq_MEMdq | VPHADDUBQ_XMMdq_XMMdq | VPHADDUBW_XMMdq_MEMdq | VPHADDUBW_XMMdq_XMMdq | VPHADDUDQ_XMMdq_MEMdq | VPHADDUDQ_XMMdq_XMMdq | VPHADDUWD_XMMdq_MEMdq | VPHADDUWD_XMMdq_XMMdq | VPHADDUWQ_XMMdq_MEMdq | VPHADDUWQ_XMMdq_XMMdq | VPHADDW_XMMdq_XMMdq_MEMdq | VPHADDW_XMMdq_XMMdq_XMMdq | VPHADDW_YMMqq_YMMqq_MEMqq | VPHADDW_YMMqq_YMMqq_YMMqq | VPHADDWD_XMMdq_MEMdq | VPHADDWD_XMMdq_XMMdq | VPHADDWQ_XMMdq_MEMdq | VPHADDWQ_XMMdq_XMMdq | VPHMINPOSUW_XMMdq_MEMdq | VPHMINPOSUW_XMMdq_XMMdq | VPHSUBBW_XMMdq_MEMdq | VPHSUBBW_XMMdq_XMMdq | VPHSUBD_XMMdq_XMMdq_MEMdq | VPHSUBD_XMMdq_XMMdq_XMMdq | VPHSUBD_YMMqq_YMMqq_MEMqq | VPHSUBD_YMMqq_YMMqq_YMMqq | VPHSUBDQ_XMMdq_MEMdq | VPHSUBDQ_XMMdq_XMMdq | VPHSUBSW_XMMdq_XMMdq_MEMdq | VPHSUBSW_XMMdq_XMMdq_XMMdq | VPHSUBSW_YMMqq_YMMqq_MEMqq | VPHSUBSW_YMMqq_YMMqq_YMMqq | VPHSUBW_XMMdq_XMMdq_MEMdq | VPHSUBW_XMMdq_XMMdq_XMMdq | VPHSUBW_YMMqq_YMMqq_MEMqq | VPHSUBW_YMMqq_YMMqq_YMMqq | VPHSUBWD_XMMdq_MEMdq | VPHSUBWD_XMMdq_XMMdq | VPINSRB_XMMdq_XMMdq_GPR32d_IMMb | VPINSRB_XMMdq_XMMdq_MEMb_IMMb | VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 | VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 | VPINSRD_XMMdq_XMMdq_GPR32d_IMMb | VPINSRD_XMMdq_XMMdq_MEMd_IMMb | VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 | VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 | VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb | VPINSRQ_XMMdq_XMMdq_MEMq_IMMb | VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 | VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 | VPINSRW_XMMdq_XMMdq_GPR32d_IMMb | VPINSRW_XMMdq_XMMdq_MEMw_IMMb | VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 | VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 | VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 | VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 | VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 | VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 | VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD | VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD | VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 | VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 | VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 | VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 | VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD | VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD | VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq | VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq | VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq | VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq | VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq | VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq | VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq | VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPMADD52HUQ_XMMu64_XMMu64_MEMu64 | VPMADD52HUQ_XMMu64_XMMu64_XMMu64 | VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPMADD52HUQ_YMMu64_YMMu64_MEMu64 | VPMADD52HUQ_YMMu64_YMMu64_YMMu64 | VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPMADD52LUQ_XMMu64_XMMu64_MEMu64 | VPMADD52LUQ_XMMu64_XMMu64_XMMu64 | VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPMADD52LUQ_YMMu64_YMMu64_MEMu64 | VPMADD52LUQ_YMMu64_YMMu64_YMMu64 | VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPMADDUBSW_XMMdq_XMMdq_MEMdq | VPMADDUBSW_XMMdq_XMMdq_XMMdq | VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 | VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 | VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 | VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 | VPMADDUBSW_YMMqq_YMMqq_MEMqq | VPMADDUBSW_YMMqq_YMMqq_YMMqq | VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 | VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPMADDWD_XMMdq_XMMdq_MEMdq | VPMADDWD_XMMdq_XMMdq_XMMdq | VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 | VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 | VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 | VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 | VPMADDWD_YMMqq_YMMqq_MEMqq | VPMADDWD_YMMqq_YMMqq_YMMqq | VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 | VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPMASKMOVD_MEMdq_XMMdq_XMMdq | VPMASKMOVD_MEMqq_YMMqq_YMMqq | VPMASKMOVD_XMMdq_XMMdq_MEMdq | VPMASKMOVD_YMMqq_YMMqq_MEMqq | VPMASKMOVQ_MEMdq_XMMdq_XMMdq | VPMASKMOVQ_MEMqq_YMMqq_YMMqq | VPMASKMOVQ_XMMdq_XMMdq_MEMdq | VPMASKMOVQ_YMMqq_YMMqq_MEMqq | VPMAXSB_XMMdq_XMMdq_MEMdq | VPMAXSB_XMMdq_XMMdq_XMMdq | VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 | VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 | VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 | VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 | VPMAXSB_YMMqq_YMMqq_MEMqq | VPMAXSB_YMMqq_YMMqq_YMMqq | VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 | VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 | VPMAXSD_XMMdq_XMMdq_MEMdq | VPMAXSD_XMMdq_XMMdq_XMMdq | VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 | VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 | VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 | VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 | VPMAXSD_YMMqq_YMMqq_MEMqq | VPMAXSD_YMMqq_YMMqq_YMMqq | VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 | VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 | VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 | VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 | VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 | VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 | VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 | VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 | VPMAXSW_XMMdq_XMMdq_MEMdq | VPMAXSW_XMMdq_XMMdq_XMMdq | VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 | VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 | VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 | VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 | VPMAXSW_YMMqq_YMMqq_MEMqq | VPMAXSW_YMMqq_YMMqq_YMMqq | VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 | VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPMAXUB_XMMdq_XMMdq_MEMdq | VPMAXUB_XMMdq_XMMdq_XMMdq | VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPMAXUB_YMMqq_YMMqq_MEMqq | VPMAXUB_YMMqq_YMMqq_YMMqq | VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPMAXUD_XMMdq_XMMdq_MEMdq | VPMAXUD_XMMdq_XMMdq_XMMdq | VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPMAXUD_YMMqq_YMMqq_MEMqq | VPMAXUD_YMMqq_YMMqq_YMMqq | VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPMAXUW_XMMdq_XMMdq_MEMdq | VPMAXUW_XMMdq_XMMdq_XMMdq | VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPMAXUW_YMMqq_YMMqq_MEMqq | VPMAXUW_YMMqq_YMMqq_YMMqq | VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPMINSB_XMMdq_XMMdq_MEMdq | VPMINSB_XMMdq_XMMdq_XMMdq | VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 | VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 | VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 | VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 | VPMINSB_YMMqq_YMMqq_MEMqq | VPMINSB_YMMqq_YMMqq_YMMqq | VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 | VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 | VPMINSD_XMMdq_XMMdq_MEMdq | VPMINSD_XMMdq_XMMdq_XMMdq | VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 | VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 | VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 | VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 | VPMINSD_YMMqq_YMMqq_MEMqq | VPMINSD_YMMqq_YMMqq_YMMqq | VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 | VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 | VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 | VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 | VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 | VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 | VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 | VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 | VPMINSW_XMMdq_XMMdq_MEMdq | VPMINSW_XMMdq_XMMdq_XMMdq | VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 | VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 | VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 | VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 | VPMINSW_YMMqq_YMMqq_MEMqq | VPMINSW_YMMqq_YMMqq_YMMqq | VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 | VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPMINUB_XMMdq_XMMdq_MEMdq | VPMINUB_XMMdq_XMMdq_XMMdq | VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPMINUB_YMMqq_YMMqq_MEMqq | VPMINUB_YMMqq_YMMqq_YMMqq | VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPMINUD_XMMdq_XMMdq_MEMdq | VPMINUD_XMMdq_XMMdq_XMMdq | VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPMINUD_YMMqq_YMMqq_MEMqq | VPMINUD_YMMqq_YMMqq_YMMqq | VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPMINUW_XMMdq_XMMdq_MEMdq | VPMINUW_XMMdq_XMMdq_XMMdq | VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPMINUW_YMMqq_YMMqq_MEMqq | VPMINUW_YMMqq_YMMqq_YMMqq | VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPMOVB2M_MASKmskw_XMMu8_AVX512 | VPMOVB2M_MASKmskw_YMMu8_AVX512 | VPMOVB2M_MASKmskw_ZMMu8_AVX512 | VPMOVD2M_MASKmskw_XMMu32_AVX512 | VPMOVD2M_MASKmskw_YMMu32_AVX512 | VPMOVD2M_MASKmskw_ZMMu32_AVX512 | VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 | VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 | VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 | VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 | VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 | VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 | VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 | VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 | VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 | VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 | VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 | VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 | VPMOVM2B_XMMu8_MASKmskw_AVX512 | VPMOVM2B_YMMu8_MASKmskw_AVX512 | VPMOVM2B_ZMMu8_MASKmskw_AVX512 | VPMOVM2D_XMMu32_MASKmskw_AVX512 | VPMOVM2D_YMMu32_MASKmskw_AVX512 | VPMOVM2D_ZMMu32_MASKmskw_AVX512 | VPMOVM2Q_XMMu64_MASKmskw_AVX512 | VPMOVM2Q_YMMu64_MASKmskw_AVX512 | VPMOVM2Q_ZMMu64_MASKmskw_AVX512 | VPMOVM2W_XMMu16_MASKmskw_AVX512 | VPMOVM2W_YMMu16_MASKmskw_AVX512 | VPMOVM2W_ZMMu16_MASKmskw_AVX512 | VPMOVMSKB_GPR32d_XMMdq | VPMOVMSKB_GPR32d_YMMqq | VPMOVQ2M_MASKmskw_XMMu64_AVX512 | VPMOVQ2M_MASKmskw_YMMu64_AVX512 | VPMOVQ2M_MASKmskw_ZMMu64_AVX512 | VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 | VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 | VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 | VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 | VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 | VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 | VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 | VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 | VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 | VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 | VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 | VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 | VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 | VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 | VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 | VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 | VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 | VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 | VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 | VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 | VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 | VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 | VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 | VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 | VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 | VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 | VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 | VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 | VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 | VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 | VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 | VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 | VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 | VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 | VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 | VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 | VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 | VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 | VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 | VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 | VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 | VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 | VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 | VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 | VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 | VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 | VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 | VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 | VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 | VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 | VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 | VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 | VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 | VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 | VPMOVSXBD_XMMdq_MEMd | VPMOVSXBD_XMMdq_XMMd | VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 | VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 | VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 | VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 | VPMOVSXBD_YMMqq_MEMq | VPMOVSXBD_YMMqq_XMMq | VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 | VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 | VPMOVSXBQ_XMMdq_MEMw | VPMOVSXBQ_XMMdq_XMMw | VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 | VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 | VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 | VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 | VPMOVSXBQ_YMMqq_MEMd | VPMOVSXBQ_YMMqq_XMMd | VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 | VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 | VPMOVSXBW_XMMdq_MEMq | VPMOVSXBW_XMMdq_XMMq | VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 | VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 | VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 | VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 | VPMOVSXBW_YMMqq_MEMdq | VPMOVSXBW_YMMqq_XMMdq | VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 | VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 | VPMOVSXDQ_XMMdq_MEMq | VPMOVSXDQ_XMMdq_XMMq | VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 | VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 | VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 | VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 | VPMOVSXDQ_YMMqq_MEMdq | VPMOVSXDQ_YMMqq_XMMdq | VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 | VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 | VPMOVSXWD_XMMdq_MEMq | VPMOVSXWD_XMMdq_XMMq | VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 | VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 | VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 | VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 | VPMOVSXWD_YMMqq_MEMdq | VPMOVSXWD_YMMqq_XMMdq | VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 | VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 | VPMOVSXWQ_XMMdq_MEMd | VPMOVSXWQ_XMMdq_XMMd | VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 | VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 | VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 | VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 | VPMOVSXWQ_YMMqq_MEMq | VPMOVSXWQ_YMMqq_XMMq | VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 | VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 | VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 | VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 | VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 | VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 | VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 | VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 | VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 | VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 | VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 | VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 | VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 | VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 | VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 | VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 | VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 | VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 | VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 | VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 | VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 | VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 | VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 | VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 | VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 | VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 | VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 | VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 | VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 | VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 | VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 | VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 | VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 | VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 | VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 | VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 | VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 | VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 | VPMOVW2M_MASKmskw_XMMu16_AVX512 | VPMOVW2M_MASKmskw_YMMu16_AVX512 | VPMOVW2M_MASKmskw_ZMMu16_AVX512 | VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 | VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 | VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 | VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 | VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 | VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 | VPMOVZXBD_XMMdq_MEMd | VPMOVZXBD_XMMdq_XMMd | VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 | VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 | VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 | VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 | VPMOVZXBD_YMMqq_MEMq | VPMOVZXBD_YMMqq_XMMq | VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 | VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 | VPMOVZXBQ_XMMdq_MEMw | VPMOVZXBQ_XMMdq_XMMw | VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 | VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 | VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 | VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 | VPMOVZXBQ_YMMqq_MEMd | VPMOVZXBQ_YMMqq_XMMd | VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 | VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 | VPMOVZXBW_XMMdq_MEMq | VPMOVZXBW_XMMdq_XMMq | VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 | VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 | VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 | VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 | VPMOVZXBW_YMMqq_MEMdq | VPMOVZXBW_YMMqq_XMMdq | VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 | VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 | VPMOVZXDQ_XMMdq_MEMq | VPMOVZXDQ_XMMdq_XMMq | VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 | VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 | VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 | VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 | VPMOVZXDQ_YMMqq_MEMdq | VPMOVZXDQ_YMMqq_XMMdq | VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 | VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 | VPMOVZXWD_XMMdq_MEMq | VPMOVZXWD_XMMdq_XMMq | VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 | VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 | VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 | VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 | VPMOVZXWD_YMMqq_MEMdq | VPMOVZXWD_YMMqq_XMMdq | VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 | VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 | VPMOVZXWQ_XMMdq_MEMd | VPMOVZXWQ_XMMdq_XMMd | VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 | VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 | VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 | VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 | VPMOVZXWQ_YMMqq_MEMq | VPMOVZXWQ_YMMqq_XMMq | VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 | VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 | VPMULDQ_XMMdq_XMMdq_MEMdq | VPMULDQ_XMMdq_XMMdq_XMMdq | VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 | VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 | VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 | VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 | VPMULDQ_YMMqq_YMMqq_MEMqq | VPMULDQ_YMMqq_YMMqq_YMMqq | VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 | VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 | VPMULHRSW_XMMdq_XMMdq_MEMdq | VPMULHRSW_XMMdq_XMMdq_XMMdq | VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 | VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 | VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 | VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 | VPMULHRSW_YMMqq_YMMqq_MEMqq | VPMULHRSW_YMMqq_YMMqq_YMMqq | VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 | VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPMULHUW_XMMdq_XMMdq_MEMdq | VPMULHUW_XMMdq_XMMdq_XMMdq | VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPMULHUW_YMMqq_YMMqq_MEMqq | VPMULHUW_YMMqq_YMMqq_YMMqq | VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPMULHW_XMMdq_XMMdq_MEMdq | VPMULHW_XMMdq_XMMdq_XMMdq | VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPMULHW_YMMqq_YMMqq_MEMqq | VPMULHW_YMMqq_YMMqq_YMMqq | VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPMULLD_XMMdq_XMMdq_MEMdq | VPMULLD_XMMdq_XMMdq_XMMdq | VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPMULLD_YMMqq_YMMqq_MEMqq | VPMULLD_YMMqq_YMMqq_YMMqq | VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPMULLW_XMMdq_XMMdq_MEMdq | VPMULLW_XMMdq_XMMdq_XMMdq | VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPMULLW_YMMqq_YMMqq_MEMqq | VPMULLW_YMMqq_YMMqq_YMMqq | VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 | VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 | VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 | VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 | VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 | VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 | VPMULUDQ_XMMdq_XMMdq_MEMdq | VPMULUDQ_XMMdq_XMMdq_XMMdq | VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 | VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 | VPMULUDQ_YMMqq_YMMqq_MEMqq | VPMULUDQ_YMMqq_YMMqq_YMMqq | VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 | VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 | VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 | VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 | VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 | VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 | VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 | VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 | VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 | VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 | VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 | VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 | VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 | VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 | VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 | VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 | VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 | VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 | VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 | VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 | VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 | VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 | VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 | VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 | VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 | VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 | VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 | VPOR_XMMdq_XMMdq_MEMdq | VPOR_XMMdq_XMMdq_XMMdq | VPOR_YMMqq_YMMqq_MEMqq | VPOR_YMMqq_YMMqq_YMMqq | VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPPERM_XMMdq_XMMdq_MEMdq_XMMdq | VPPERM_XMMdq_XMMdq_XMMdq_MEMdq | VPPERM_XMMdq_XMMdq_XMMdq_XMMdq | VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 | VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 | VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 | VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 | VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 | VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 | VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 | VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 | VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPROTB_XMMdq_MEMdq_IMMb | VPROTB_XMMdq_MEMdq_XMMdq | VPROTB_XMMdq_XMMdq_IMMb | VPROTB_XMMdq_XMMdq_MEMdq | VPROTB_XMMdq_XMMdq_XMMdq | VPROTD_XMMdq_MEMdq_IMMb | VPROTD_XMMdq_MEMdq_XMMdq | VPROTD_XMMdq_XMMdq_IMMb | VPROTD_XMMdq_XMMdq_MEMdq | VPROTD_XMMdq_XMMdq_XMMdq | VPROTQ_XMMdq_MEMdq_IMMb | VPROTQ_XMMdq_MEMdq_XMMdq | VPROTQ_XMMdq_XMMdq_IMMb | VPROTQ_XMMdq_XMMdq_MEMdq | VPROTQ_XMMdq_XMMdq_XMMdq | VPROTW_XMMdq_MEMdq_IMMb | VPROTW_XMMdq_MEMdq_XMMdq | VPROTW_XMMdq_XMMdq_IMMb | VPROTW_XMMdq_XMMdq_MEMdq | VPROTW_XMMdq_XMMdq_XMMdq | VPSADBW_XMMdq_XMMdq_MEMdq | VPSADBW_XMMdq_XMMdq_XMMdq | VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 | VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 | VPSADBW_YMMqq_YMMqq_MEMqq | VPSADBW_YMMqq_YMMqq_YMMqq | VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 | VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 | VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 | VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 | VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 | VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 | VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 | VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 | VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 | VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 | VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 | VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 | VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 | VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 | VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 | VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 | VPSHAB_XMMdq_MEMdq_XMMdq | VPSHAB_XMMdq_XMMdq_MEMdq | VPSHAB_XMMdq_XMMdq_XMMdq | VPSHAD_XMMdq_MEMdq_XMMdq | VPSHAD_XMMdq_XMMdq_MEMdq | VPSHAD_XMMdq_XMMdq_XMMdq | VPSHAQ_XMMdq_MEMdq_XMMdq | VPSHAQ_XMMdq_XMMdq_MEMdq | VPSHAQ_XMMdq_XMMdq_XMMdq | VPSHAW_XMMdq_MEMdq_XMMdq | VPSHAW_XMMdq_XMMdq_MEMdq | VPSHAW_XMMdq_XMMdq_XMMdq | VPSHLB_XMMdq_MEMdq_XMMdq | VPSHLB_XMMdq_XMMdq_MEMdq | VPSHLB_XMMdq_XMMdq_XMMdq | VPSHLD_XMMdq_MEMdq_XMMdq | VPSHLD_XMMdq_XMMdq_MEMdq | VPSHLD_XMMdq_XMMdq_XMMdq | VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 | VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 | VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 | VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 | VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 | VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 | VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 | VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 | VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 | VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 | VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 | VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 | VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 | VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 | VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 | VPSHLQ_XMMdq_MEMdq_XMMdq | VPSHLQ_XMMdq_XMMdq_MEMdq | VPSHLQ_XMMdq_XMMdq_XMMdq | VPSHLW_XMMdq_MEMdq_XMMdq | VPSHLW_XMMdq_XMMdq_MEMdq | VPSHLW_XMMdq_XMMdq_XMMdq | VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 | VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 | VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 | VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 | VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 | VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 | VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 | VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 | VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 | VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 | VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 | VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 | VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 | VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 | VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 | VPSHUFB_XMMdq_XMMdq_MEMdq | VPSHUFB_XMMdq_XMMdq_XMMdq | VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPSHUFB_YMMqq_YMMqq_MEMqq | VPSHUFB_YMMqq_YMMqq_YMMqq | VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 | VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 | VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 | VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 | VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 | VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 | VPSHUFD_XMMdq_MEMdq_IMMb | VPSHUFD_XMMdq_XMMdq_IMMb | VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 | VPSHUFD_YMMqq_MEMqq_IMMb | VPSHUFD_YMMqq_YMMqq_IMMb | VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 | VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VPSHUFHW_XMMdq_MEMdq_IMMb | VPSHUFHW_XMMdq_XMMdq_IMMb | VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 | VPSHUFHW_YMMqq_MEMqq_IMMb | VPSHUFHW_YMMqq_YMMqq_IMMb | VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 | VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 | VPSHUFLW_XMMdq_MEMdq_IMMb | VPSHUFLW_XMMdq_XMMdq_IMMb | VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 | VPSHUFLW_YMMqq_MEMqq_IMMb | VPSHUFLW_YMMqq_YMMqq_IMMb | VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 | VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 | VPSIGNB_XMMdq_XMMdq_MEMdq | VPSIGNB_XMMdq_XMMdq_XMMdq | VPSIGNB_YMMqq_YMMqq_MEMqq | VPSIGNB_YMMqq_YMMqq_YMMqq | VPSIGND_XMMdq_XMMdq_MEMdq | VPSIGND_XMMdq_XMMdq_XMMdq | VPSIGND_YMMqq_YMMqq_MEMqq | VPSIGND_YMMqq_YMMqq_YMMqq | VPSIGNW_XMMdq_XMMdq_MEMdq | VPSIGNW_XMMdq_XMMdq_XMMdq | VPSIGNW_YMMqq_YMMqq_MEMqq | VPSIGNW_YMMqq_YMMqq_YMMqq | VPSLLD_XMMdq_XMMdq_IMMb | VPSLLD_XMMdq_XMMdq_MEMdq | VPSLLD_XMMdq_XMMdq_XMMdq | VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 | VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSLLD_YMMqq_YMMqq_IMMb | VPSLLD_YMMqq_YMMqq_MEMdq | VPSLLD_YMMqq_YMMqq_XMMq | VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 | VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 | VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 | VPSLLDQ_XMMdq_XMMdq_IMMb | VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 | VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 | VPSLLDQ_YMMqq_YMMqq_IMMb | VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 | VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 | VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 | VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 | VPSLLQ_XMMdq_XMMdq_IMMb | VPSLLQ_XMMdq_XMMdq_MEMdq | VPSLLQ_XMMdq_XMMdq_XMMdq | VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 | VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSLLQ_YMMqq_YMMqq_IMMb | VPSLLQ_YMMqq_YMMqq_MEMdq | VPSLLQ_YMMqq_YMMqq_XMMq | VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 | VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 | VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 | VPSLLVD_XMMdq_XMMdq_MEMdq | VPSLLVD_XMMdq_XMMdq_XMMdq | VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSLLVD_YMMqq_YMMqq_MEMqq | VPSLLVD_YMMqq_YMMqq_YMMqq | VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPSLLVQ_XMMdq_XMMdq_MEMdq | VPSLLVQ_XMMdq_XMMdq_XMMdq | VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSLLVQ_YMMqq_YMMqq_MEMqq | VPSLLVQ_YMMqq_YMMqq_YMMqq | VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPSLLW_XMMdq_XMMdq_IMMb | VPSLLW_XMMdq_XMMdq_MEMdq | VPSLLW_XMMdq_XMMdq_XMMdq | VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 | VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSLLW_YMMqq_YMMqq_IMMb | VPSLLW_YMMqq_YMMqq_MEMdq | VPSLLW_YMMqq_YMMqq_XMMq | VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 | VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 | VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 | VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 | VPSRAD_XMMdq_XMMdq_IMMb | VPSRAD_XMMdq_XMMdq_MEMdq | VPSRAD_XMMdq_XMMdq_XMMdq | VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 | VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSRAD_YMMqq_YMMqq_IMMb | VPSRAD_YMMqq_YMMqq_MEMdq | VPSRAD_YMMqq_YMMqq_XMMq | VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 | VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 | VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 | VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 | VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 | VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 | VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 | VPSRAVD_XMMdq_XMMdq_MEMdq | VPSRAVD_XMMdq_XMMdq_XMMdq | VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSRAVD_YMMqq_YMMqq_MEMqq | VPSRAVD_YMMqq_YMMqq_YMMqq | VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPSRAW_XMMdq_XMMdq_IMMb | VPSRAW_XMMdq_XMMdq_MEMdq | VPSRAW_XMMdq_XMMdq_XMMdq | VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 | VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSRAW_YMMqq_YMMqq_IMMb | VPSRAW_YMMqq_YMMqq_MEMdq | VPSRAW_YMMqq_YMMqq_XMMq | VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 | VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 | VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 | VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 | VPSRLD_XMMdq_XMMdq_IMMb | VPSRLD_XMMdq_XMMdq_MEMdq | VPSRLD_XMMdq_XMMdq_XMMdq | VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 | VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSRLD_YMMqq_YMMqq_IMMb | VPSRLD_YMMqq_YMMqq_MEMdq | VPSRLD_YMMqq_YMMqq_XMMq | VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 | VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 | VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 | VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 | VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 | VPSRLDQ_XMMdq_XMMdq_IMMb | VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 | VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 | VPSRLDQ_YMMqq_YMMqq_IMMb | VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 | VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 | VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 | VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 | VPSRLQ_XMMdq_XMMdq_IMMb | VPSRLQ_XMMdq_XMMdq_MEMdq | VPSRLQ_XMMdq_XMMdq_XMMdq | VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 | VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSRLQ_YMMqq_YMMqq_IMMb | VPSRLQ_YMMqq_YMMqq_MEMdq | VPSRLQ_YMMqq_YMMqq_XMMq | VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 | VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 | VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 | VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 | VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 | VPSRLVD_XMMdq_XMMdq_MEMdq | VPSRLVD_XMMdq_XMMdq_XMMdq | VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSRLVD_YMMqq_YMMqq_MEMqq | VPSRLVD_YMMqq_YMMqq_YMMqq | VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPSRLVQ_XMMdq_XMMdq_MEMdq | VPSRLVQ_XMMdq_XMMdq_XMMdq | VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSRLVQ_YMMqq_YMMqq_MEMqq | VPSRLVQ_YMMqq_YMMqq_YMMqq | VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPSRLW_XMMdq_XMMdq_IMMb | VPSRLW_XMMdq_XMMdq_MEMdq | VPSRLW_XMMdq_XMMdq_XMMdq | VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 | VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSRLW_YMMqq_YMMqq_IMMb | VPSRLW_YMMqq_YMMqq_MEMdq | VPSRLW_YMMqq_YMMqq_XMMq | VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 | VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 | VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 | VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 | VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 | VPSUBB_XMMdq_XMMdq_MEMdq | VPSUBB_XMMdq_XMMdq_XMMdq | VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPSUBB_YMMqq_YMMqq_MEMqq | VPSUBB_YMMqq_YMMqq_YMMqq | VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPSUBD_XMMdq_XMMdq_MEMdq | VPSUBD_XMMdq_XMMdq_XMMdq | VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPSUBD_YMMqq_YMMqq_MEMqq | VPSUBD_YMMqq_YMMqq_YMMqq | VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPSUBQ_XMMdq_XMMdq_MEMdq | VPSUBQ_XMMdq_XMMdq_XMMdq | VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPSUBQ_YMMqq_YMMqq_MEMqq | VPSUBQ_YMMqq_YMMqq_YMMqq | VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPSUBSB_XMMdq_XMMdq_MEMdq | VPSUBSB_XMMdq_XMMdq_XMMdq | VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 | VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 | VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 | VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 | VPSUBSB_YMMqq_YMMqq_MEMqq | VPSUBSB_YMMqq_YMMqq_YMMqq | VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 | VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 | VPSUBSW_XMMdq_XMMdq_MEMdq | VPSUBSW_XMMdq_XMMdq_XMMdq | VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 | VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 | VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 | VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 | VPSUBSW_YMMqq_YMMqq_MEMqq | VPSUBSW_YMMqq_YMMqq_YMMqq | VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 | VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 | VPSUBUSB_XMMdq_XMMdq_MEMdq | VPSUBUSB_XMMdq_XMMdq_XMMdq | VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPSUBUSB_YMMqq_YMMqq_MEMqq | VPSUBUSB_YMMqq_YMMqq_YMMqq | VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPSUBUSW_XMMdq_XMMdq_MEMdq | VPSUBUSW_XMMdq_XMMdq_XMMdq | VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSUBUSW_YMMqq_YMMqq_MEMqq | VPSUBUSW_YMMqq_YMMqq_YMMqq | VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPSUBW_XMMdq_XMMdq_MEMdq | VPSUBW_XMMdq_XMMdq_XMMdq | VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPSUBW_YMMqq_YMMqq_MEMqq | VPSUBW_YMMqq_YMMqq_YMMqq | VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 | VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 | VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 | VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 | VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 | VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 | VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 | VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 | VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 | VPTEST_XMMdq_MEMdq | VPTEST_XMMdq_XMMdq | VPTEST_YMMqq_MEMqq | VPTEST_YMMqq_YMMqq | VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 | VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 | VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 | VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 | VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 | VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 | VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 | VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 | VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 | VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 | VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 | VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 | VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 | VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 | VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 | VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 | VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 | VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 | VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 | VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 | VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 | VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 | VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 | VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 | VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 | VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 | VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 | VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 | VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 | VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 | VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 | VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 | VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 | VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 | VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 | VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 | VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 | VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 | VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 | VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 | VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPUNPCKHBW_XMMdq_XMMdq_MEMdq | VPUNPCKHBW_XMMdq_XMMdq_XMMdq | VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPUNPCKHBW_YMMqq_YMMqq_MEMqq | VPUNPCKHBW_YMMqq_YMMqq_YMMqq | VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPUNPCKHDQ_XMMdq_XMMdq_MEMdq | VPUNPCKHDQ_XMMdq_XMMdq_XMMdq | VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPUNPCKHDQ_YMMqq_YMMqq_MEMqq | VPUNPCKHDQ_YMMqq_YMMqq_YMMqq | VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq | VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq | VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq | VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq | VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPUNPCKHWD_XMMdq_XMMdq_MEMdq | VPUNPCKHWD_XMMdq_XMMdq_XMMdq | VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPUNPCKHWD_YMMqq_YMMqq_MEMqq | VPUNPCKHWD_YMMqq_YMMqq_YMMqq | VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPUNPCKLBW_XMMdq_XMMdq_MEMdq | VPUNPCKLBW_XMMdq_XMMdq_XMMdq | VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 | VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 | VPUNPCKLBW_YMMqq_YMMqq_MEMqq | VPUNPCKLBW_YMMqq_YMMqq_YMMqq | VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 | VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 | VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 | VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 | VPUNPCKLDQ_XMMdq_XMMdq_MEMdq | VPUNPCKLDQ_XMMdq_XMMdq_XMMdq | VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPUNPCKLDQ_YMMqq_YMMqq_MEMqq | VPUNPCKLDQ_YMMqq_YMMqq_YMMqq | VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq | VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq | VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq | VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq | VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VPUNPCKLWD_XMMdq_XMMdq_MEMdq | VPUNPCKLWD_XMMdq_XMMdq_XMMdq | VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 | VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 | VPUNPCKLWD_YMMqq_YMMqq_MEMqq | VPUNPCKLWD_YMMqq_YMMqq_YMMqq | VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 | VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 | VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 | VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 | VPXOR_XMMdq_XMMdq_MEMdq | VPXOR_XMMdq_XMMdq_XMMdq | VPXOR_YMMqq_YMMqq_MEMqq | VPXOR_YMMqq_YMMqq_YMMqq | VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 | VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 | VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 | VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 | VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 | VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 | VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 | VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 | VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 | VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 | VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 | VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 | VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 | VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 | VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 | VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 | VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER | VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER | VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER | VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER | VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER | VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER | VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER | VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER | VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 | VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 | VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 | VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 | VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 | VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 | VRCPPS_XMMdq_MEMdq | VRCPPS_XMMdq_XMMdq | VRCPPS_YMMqq_MEMqq | VRCPPS_YMMqq_YMMqq | VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VRCPSS_XMMdq_XMMdq_MEMd | VRCPSS_XMMdq_XMMdq_XMMd | VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 | VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 | VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 | VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 | VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 | VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 | VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 | VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 | VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 | VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 | VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 | VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 | VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 | VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 | VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 | VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 | VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 | VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 | VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 | VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 | VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 | VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 | VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 | VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VROUNDPD_XMMdq_MEMdq_IMMb | VROUNDPD_XMMdq_XMMdq_IMMb | VROUNDPD_YMMqq_MEMqq_IMMb | VROUNDPD_YMMqq_YMMqq_IMMb | VROUNDPS_XMMdq_MEMdq_IMMb | VROUNDPS_XMMdq_XMMdq_IMMb | VROUNDPS_YMMqq_MEMqq_IMMb | VROUNDPS_YMMqq_YMMqq_IMMb | VROUNDSD_XMMdq_XMMdq_MEMq_IMMb | VROUNDSD_XMMdq_XMMdq_XMMq_IMMb | VROUNDSS_XMMdq_XMMdq_MEMd_IMMb | VROUNDSS_XMMdq_XMMdq_XMMd_IMMb | VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 | VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 | VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 | VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 | VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 | VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 | VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 | VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 | VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 | VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 | VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER | VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER | VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER | VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER | VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER | VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER | VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER | VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER | VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 | VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 | VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 | VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 | VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 | VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 | VRSQRTPS_XMMdq_MEMdq | VRSQRTPS_XMMdq_XMMdq | VRSQRTPS_YMMqq_MEMqq | VRSQRTPS_YMMqq_YMMqq | VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VRSQRTSS_XMMdq_XMMdq_MEMd | VRSQRTSS_XMMdq_XMMdq_XMMd | VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 | VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 | VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 | VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 | VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 | VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 | VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 | VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 | VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 | VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 | VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 | VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 | VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 | VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 | VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 | VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 | VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 | VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 | VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 | VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 | VSHA512MSG1_YMMu64_XMMu64 | VSHA512MSG2_YMMu64_YMMu64 | VSHA512RNDS2_YMMu64_YMMu64_XMMu64 | VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 | VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 | VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 | VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 | VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 | VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 | VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 | VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 | VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 | VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 | VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 | VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 | VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb | VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb | VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 | VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 | VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 | VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 | VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb | VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb | VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 | VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb | VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb | VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 | VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 | VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb | VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb | VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 | VSM3MSG1_XMMu32_XMMu32_MEMu32 | VSM3MSG1_XMMu32_XMMu32_XMMu32 | VSM3MSG2_XMMu32_XMMu32_MEMu32 | VSM3MSG2_XMMu32_XMMu32_XMMu32 | VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8 | VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8 | VSM4KEY4_XMMu32_XMMu32_MEMu32 | VSM4KEY4_XMMu32_XMMu32_XMMu32 | VSM4KEY4_YMMu32_YMMu32_MEMu32 | VSM4KEY4_YMMu32_YMMu32_YMMu32 | VSM4RNDS4_XMMu32_XMMu32_MEMu32 | VSM4RNDS4_XMMu32_XMMu32_XMMu32 | VSM4RNDS4_YMMu32_YMMu32_MEMu32 | VSM4RNDS4_YMMu32_YMMu32_YMMu32 | VSQRTPD_XMMdq_MEMdq | VSQRTPD_XMMdq_XMMdq | VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 | VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 | VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 | VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 | VSQRTPD_YMMqq_MEMqq | VSQRTPD_YMMqq_YMMqq | VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 | VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 | VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 | VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 | VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 | VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 | VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 | VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 | VSQRTPS_XMMdq_MEMdq | VSQRTPS_XMMdq_XMMdq | VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 | VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 | VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 | VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 | VSQRTPS_YMMqq_MEMqq | VSQRTPS_YMMqq_YMMqq | VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 | VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 | VSQRTSD_XMMdq_XMMdq_MEMq | VSQRTSD_XMMdq_XMMdq_XMMq | VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VSQRTSS_XMMdq_XMMdq_MEMd | VSQRTSS_XMMdq_XMMdq_XMMd | VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VSTMXCSR_MEMd | VSUBPD_XMMdq_XMMdq_MEMdq | VSUBPD_XMMdq_XMMdq_XMMdq | VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VSUBPD_YMMqq_YMMqq_MEMqq | VSUBPD_YMMqq_YMMqq_YMMqq | VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | VSUBPS_XMMdq_XMMdq_MEMdq | VSUBPS_XMMdq_XMMdq_XMMdq | VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VSUBPS_YMMqq_YMMqq_MEMqq | VSUBPS_YMMqq_YMMqq_YMMqq | VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VSUBSD_XMMdq_XMMdq_MEMq | VSUBSD_XMMdq_XMMdq_XMMq | VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | VSUBSS_XMMdq_XMMdq_MEMd | VSUBSS_XMMdq_XMMdq_XMMd | VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VTESTPD_XMMdq_MEMdq | VTESTPD_XMMdq_XMMdq | VTESTPD_YMMqq_MEMqq | VTESTPD_YMMqq_YMMqq | VTESTPS_XMMdq_MEMdq | VTESTPS_XMMdq_XMMdq | VTESTPS_YMMqq_MEMqq | VTESTPS_YMMqq_YMMqq | VUCOMISD_XMMdq_MEMq | VUCOMISD_XMMdq_XMMq | VUCOMISD_XMMf64_MEMf64_AVX512 | VUCOMISD_XMMf64_XMMf64_AVX512 | VUCOMISH_XMMf16_MEMf16_AVX512 | VUCOMISH_XMMf16_XMMf16_AVX512 | VUCOMISS_XMMdq_MEMd | VUCOMISS_XMMdq_XMMd | VUCOMISS_XMMf32_MEMf32_AVX512 | VUCOMISS_XMMf32_XMMf32_AVX512 | VUNPCKHPD_XMMdq_XMMdq_MEMdq | VUNPCKHPD_XMMdq_XMMdq_XMMdq | VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VUNPCKHPD_YMMqq_YMMqq_MEMqq | VUNPCKHPD_YMMqq_YMMqq_YMMqq | VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VUNPCKHPS_XMMdq_XMMdq_MEMdq | VUNPCKHPS_XMMdq_XMMdq_XMMdq | VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VUNPCKHPS_YMMqq_YMMqq_MEMqq | VUNPCKHPS_YMMqq_YMMqq_YMMqq | VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VUNPCKLPD_XMMdq_XMMdq_MEMdq | VUNPCKLPD_XMMdq_XMMdq_XMMdq | VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 | VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 | VUNPCKLPD_YMMqq_YMMqq_MEMqq | VUNPCKLPD_YMMqq_YMMqq_YMMqq | VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 | VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 | VUNPCKLPS_XMMdq_XMMdq_MEMdq | VUNPCKLPS_XMMdq_XMMdq_XMMdq | VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 | VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 | VUNPCKLPS_YMMqq_YMMqq_MEMqq | VUNPCKLPS_YMMqq_YMMqq_YMMqq | VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 | VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 | VXORPD_XMMdq_XMMdq_MEMdq | VXORPD_XMMdq_XMMdq_XMMdq | VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 | VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 | VXORPD_YMMqq_YMMqq_MEMqq | VXORPD_YMMqq_YMMqq_YMMqq | VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 | VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 | VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 | VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 | VXORPS_XMMdq_XMMdq_MEMdq | VXORPS_XMMdq_XMMdq_XMMdq | VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 | VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 | VXORPS_YMMqq_YMMqq_MEMqq | VXORPS_YMMqq_YMMqq_YMMqq | VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 | VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 | VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 | VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 | VZEROALL | VZEROUPPER | WBINVD | WBNOINVD | WRFSBASE_GPRy | WRGSBASE_GPRy | WRMSR | WRMSRLIST | WRMSRNS | WRPKRU | WRSSD_MEMu32_GPR32u32 | WRSSD_MEMu32_GPR32u32_APX | WRSSQ_MEMu64_GPR64u64 | WRSSQ_MEMu64_GPR64u64_APX | WRUSSD_MEMu32_GPR32u32 | WRUSSD_MEMu32_GPR32u32_APX | WRUSSQ_MEMu64_GPR64u64 | WRUSSQ_MEMu64_GPR64u64_APX | XABORT_IMMb | XADD_GPR8_GPR8 | XADD_GPRv_GPRv | XADD_MEMb_GPR8 | XADD_MEMv_GPRv | XADD_LOCK_MEMb_GPR8 | XADD_LOCK_MEMv_GPRv | XBEGIN_RELBRz | XCHG_GPR8_GPR8 | XCHG_GPRv_GPRv | XCHG_GPRv_OrAX | XCHG_MEMb_GPR8 | XCHG_MEMv_GPRv | XEND | XGETBV | XLAT | XOR_AL_IMMb | XOR_GPR8_GPR8_30 | XOR_GPR8_GPR8_32 | XOR_GPR8_IMMb_80r6 | XOR_GPR8_IMMb_82r6 | XOR_GPR8_MEMb | XOR_GPR8i8_GPR8i8_APX | XOR_GPR8i8_GPR8i8_GPR8i8_APX | XOR_GPR8i8_GPR8i8_IMM8_APX | XOR_GPR8i8_GPR8i8_MEMi8_APX | XOR_GPR8i8_IMM8_APX | XOR_GPR8i8_MEMi8_APX | XOR_GPR8i8_MEMi8_GPR8i8_APX | XOR_GPR8i8_MEMi8_IMM8_APX | XOR_GPRv_GPRv_31 | XOR_GPRv_GPRv_33 | XOR_GPRv_GPRv_APX | XOR_GPRv_GPRv_GPRv_APX | XOR_GPRv_GPRv_IMM8_APX | XOR_GPRv_GPRv_IMMz_APX | XOR_GPRv_GPRv_MEMv_APX | XOR_GPRv_IMM8_APX | XOR_GPRv_IMMb | XOR_GPRv_IMMz | XOR_GPRv_IMMz_APX | XOR_GPRv_MEMv | XOR_GPRv_MEMv_APX | XOR_GPRv_MEMv_GPRv_APX | XOR_GPRv_MEMv_IMM8_APX | XOR_GPRv_MEMv_IMMz_APX | XOR_MEMb_GPR8 | XOR_MEMb_IMMb_80r6 | XOR_MEMb_IMMb_82r6 | XOR_MEMi8_GPR8i8_APX | XOR_MEMi8_IMM8_APX | XOR_MEMv_GPRv | XOR_MEMv_GPRv_APX | XOR_MEMv_IMM8_APX | XOR_MEMv_IMMb | XOR_MEMv_IMMz | XOR_MEMv_IMMz_APX | XOR_OrAX_IMMz | XORPD_XMMxuq_MEMxuq | XORPD_XMMxuq_XMMxuq | XORPS_XMMxud_MEMxud | XORPS_XMMxud_XMMxud | XOR_LOCK_MEMb_GPR8 | XOR_LOCK_MEMb_IMMb_80r6 | XOR_LOCK_MEMb_IMMb_82r6 | XOR_LOCK_MEMv_GPRv | XOR_LOCK_MEMv_IMMb | XOR_LOCK_MEMv_IMMz | XRESLDTRK | XRSTOR_MEMmxsave | XRSTOR64_MEMmxsave | XRSTORS_MEMmxsave | XRSTORS64_MEMmxsave | XSAVE_MEMmxsave | XSAVE64_MEMmxsave | XSAVEC_MEMmxsave | XSAVEC64_MEMmxsave | XSAVEOPT_MEMmxsave | XSAVEOPT64_MEMmxsave | XSAVES_MEMmxsave | XSAVES64_MEMmxsave | XSETBV | XSTORE | XSUSLDTRK | XTEST let iform_len = 8086 let iform_to_int : iform -> int = Obj.magic let iform_of_int (x : int) : iform = if 0 <= x && x < 8086 then Obj.magic x else failwith "iform_of_int: no enum for given int" type isa_set = | INVALID | AMD3DNOW | ADOX_ADCX | AES | AMD | AMD_INVLPGB | AMX_BF16 | AMX_COMPLEX | AMX_FP16 | AMX_INT8 | AMX_TILE | APX_F | APX_F_ADX | APX_F_AMX | APX_F_BMI1 | APX_F_BMI2 | APX_F_CET | APX_F_CMPCCXADD | APX_F_ENQCMD | APX_F_INVPCID | APX_F_KOPB | APX_F_KOPD | APX_F_KOPQ | APX_F_KOPW | APX_F_LZCNT | APX_F_MOVBE | APX_F_MOVDIR64B | APX_F_MOVDIRI | APX_F_POPCNT | APX_F_RAO_INT | APX_F_USER_MSR | APX_F_VMX | AVX | AVX2 | AVX2GATHER | AVX512BW_128 | AVX512BW_128N | AVX512BW_256 | AVX512BW_512 | AVX512BW_KOPD | AVX512BW_KOPQ | AVX512CD_128 | AVX512CD_256 | AVX512CD_512 | AVX512DQ_128 | AVX512DQ_128N | AVX512DQ_256 | AVX512DQ_512 | AVX512DQ_KOPB | AVX512DQ_KOPW | AVX512DQ_SCALAR | AVX512ER_512 | AVX512ER_SCALAR | AVX512F_128 | AVX512F_128N | AVX512F_256 | AVX512F_512 | AVX512F_KOPW | AVX512F_SCALAR | AVX512PF_512 | AVX512_4FMAPS_512 | AVX512_4FMAPS_SCALAR | AVX512_4VNNIW_512 | AVX512_BF16_128 | AVX512_BF16_256 | AVX512_BF16_512 | AVX512_BITALG_128 | AVX512_BITALG_256 | AVX512_BITALG_512 | AVX512_FP16_128 | AVX512_FP16_128N | AVX512_FP16_256 | AVX512_FP16_512 | AVX512_FP16_SCALAR | AVX512_GFNI_128 | AVX512_GFNI_256 | AVX512_GFNI_512 | AVX512_IFMA_128 | AVX512_IFMA_256 | AVX512_IFMA_512 | AVX512_VAES_128 | AVX512_VAES_256 | AVX512_VAES_512 | AVX512_VBMI2_128 | AVX512_VBMI2_256 | AVX512_VBMI2_512 | AVX512_VBMI_128 | AVX512_VBMI_256 | AVX512_VBMI_512 | AVX512_VNNI_128 | AVX512_VNNI_256 | AVX512_VNNI_512 | AVX512_VP2INTERSECT_128 | AVX512_VP2INTERSECT_256 | AVX512_VP2INTERSECT_512 | AVX512_VPCLMULQDQ_128 | AVX512_VPCLMULQDQ_256 | AVX512_VPCLMULQDQ_512 | AVX512_VPOPCNTDQ_128 | AVX512_VPOPCNTDQ_256 | AVX512_VPOPCNTDQ_512 | AVXAES | AVX_GFNI | AVX_IFMA | AVX_NE_CONVERT | AVX_VNNI | AVX_VNNI_INT16 | AVX_VNNI_INT8 | BMI1 | BMI2 | CET | CLDEMOTE | CLFLUSHOPT | CLFSH | CLWB | CLZERO | CMOV | CMPCCXADD | CMPXCHG16B | ENQCMD | F16C | FAT_NOP | FCMOV | FCOMI | FMA | FMA4 | FRED | FXSAVE | FXSAVE64 | GFNI | HRESET | I186 | I286PROTECTED | I286REAL | I386 | I486 | I486REAL | I86 | ICACHE_PREFETCH | INVPCID | KEYLOCKER | KEYLOCKER_WIDE | LAHF | LKGS | LONGMODE | LWP | LZCNT | MCOMMIT | MONITOR | MONITORX | MOVBE | MOVDIR64B | MOVDIRI | MPX | MSRLIST | PAUSE | PBNDKB | PCLMULQDQ | PCONFIG | PENTIUMMMX | PENTIUMREAL | PKU | POPCNT | PPRO | PPRO_UD0_LONG | PPRO_UD0_SHORT | PREFETCHW | PREFETCHWT1 | PREFETCH_NOP | PTWRITE | RAO_INT | RDPID | RDPMC | RDPRU | RDRAND | RDSEED | RDTSCP | RDWRFSGS | RTM | SEP | SERIALIZE | SGX | SGX_ENCLV | SHA | SHA512 | SM3 | SM4 | SMAP | SMX | SNP | SSE | SSE2 | SSE2MMX | SSE3 | SSE3X87 | SSE4 | SSE42 | SSE4A | SSEMXCSR | SSE_PREFETCH | SSSE3 | SSSE3MMX | SVM | TBM | TDX | TSX_LDTRK | UINTR | USER_MSR | VAES | VIA_PADLOCK_AES | VIA_PADLOCK_MONTMUL | VIA_PADLOCK_RNG | VIA_PADLOCK_SHA | VMFUNC | VPCLMULQDQ | VTX | WAITPKG | WBNOINVD | WRMSRNS | X87 | XOP | XSAVE | XSAVEC | XSAVEOPT | XSAVES let isa_set_len = 225 let isa_set_to_int : isa_set -> int = Obj.magic let isa_set_of_int (x : int) : isa_set = if 0 <= x && x < 225 then Obj.magic x else failwith "isa_set_of_int: no enum for given int" type machine_mode = | INVALID | LONG_64 | LONG_COMPAT_32 | LONG_COMPAT_16 | LEGACY_32 | LEGACY_16 | REAL_16 | REAL_32 let machine_mode_len = 8 let machine_mode_to_int : machine_mode -> int = Obj.magic let machine_mode_of_int (x : int) : machine_mode = if 0 <= x && x < 8 then Obj.magic x else failwith "machine_mode_of_int: no enum for given int" type nonterminal = | INVALID | AR10 | AR11 | AR12 | AR13 | AR14 | AR15 | AR16 | AR17 | AR18 | AR19 | AR20 | AR21 | AR22 | AR23 | AR24 | AR25 | AR26 | AR27 | AR28 | AR29 | AR30 | AR31 | AR8 | AR9 | ARAX | ARBP | ARBX | ARCX | ARDI | ARDX | ARSI | ARSP | ASZ_NONTERM | AVX512_ROUND | AVX_INSTRUCTIONS | AVX_SPLITTER | A_GPR_B | A_GPR_R | BND_B | BND_B_CHECK | BND_R | BND_R_CHECK | BRANCH_HINT | BRDISP32 | BRDISP64 | BRDISP8 | BRDISPZ | CET_NO_TRACK | CR_B | CR_R | CR_WIDTH | DF64 | DFV | DR_R | ESIZE_128_BITS | ESIZE_16_BITS | ESIZE_1_BITS | ESIZE_2_BITS | ESIZE_32_BITS | ESIZE_4_BITS | ESIZE_64_BITS | ESIZE_8_BITS | EVAPX | EVAPX_SCC | EVEXR4_ONE | EVEX_INSTRUCTIONS | EVEX_SPLITTER | FINAL_DSEG | FINAL_DSEG1 | FINAL_DSEG1_MODE64 | FINAL_DSEG1_NOT64 | FINAL_DSEG_MODE64 | FINAL_DSEG_NOT64 | FINAL_ESEG | FINAL_ESEG1 | FINAL_SSEG | FINAL_SSEG0 | FINAL_SSEG1 | FINAL_SSEG_MODE64 | FINAL_SSEG_NOT64 | FIX_ROUND_LEN128 | FIX_ROUND_LEN512 | FORCE64 | GPR16_B | GPR16_N | GPR16_R | GPR16_SB | GPR32_B | GPR32_N | GPR32_R | GPR32_SB | GPR64_B | GPR64_B_NORSP | GPR64_N | GPR64_N_NORSP | GPR64_R | GPR64_SB | GPR8_B | GPR8_N | GPR8_R | GPR8_SB | GPRV_B | GPRV_N | GPRV_R | GPRV_SB | GPRY_B | GPRY_R | GPRZ_B | GPRZ_R | IGNORE66 | IMMUNE66 | IMMUNE66_LOOP64 | IMMUNE_REXW | INSTRUCTIONS | ISA | MASK1 | MASKNOT0 | MASK_B | MASK_N | MASK_N32 | MASK_N64 | MASK_R | MEMDISP | MEMDISP16 | MEMDISP32 | MEMDISP8 | MEMDISPV | MMX_B | MMX_R | MODRM | MODRM16 | MODRM32 | MODRM64ALT32 | NELEM_EIGHTHMEM | NELEM_FULL | NELEM_FULLMEM | NELEM_GPR_READER | NELEM_GPR_READER_BYTE | NELEM_GPR_READER_SUBDWORD | NELEM_GPR_READER_WORD | NELEM_GPR_WRITER_LDOP | NELEM_GPR_WRITER_LDOP_D | NELEM_GPR_WRITER_LDOP_Q | NELEM_GPR_WRITER_STORE | NELEM_GPR_WRITER_STORE_BYTE | NELEM_GPR_WRITER_STORE_SUBDWORD | NELEM_GPR_WRITER_STORE_WORD | NELEM_GSCAT | NELEM_HALF | NELEM_HALFMEM | NELEM_MEM128 | NELEM_MOVDDUP | NELEM_QUARTER | NELEM_QUARTERMEM | NELEM_SCALAR | NELEM_TUPLE1 | NELEM_TUPLE1_4X | NELEM_TUPLE1_BYTE | NELEM_TUPLE1_SUBDWORD | NELEM_TUPLE1_WORD | NELEM_TUPLE2 | NELEM_TUPLE4 | NELEM_TUPLE8 | OEAX | ONE | ORAX | ORBP | ORBX | ORCX | ORDX | ORSP | OSZ_NONTERM | OVERRIDE_SEG0 | OVERRIDE_SEG1 | PREFIXES | REFINING66 | REMOVE_SEGMENT | RFLAGS | RIP | RIPA | SAE | SEG | SEG_MOV | SE_IMM8 | SIB | SIB_BASE0 | SIMM8 | SIMMZ | SRBP | SRSP | TMM_B | TMM_N | TMM_R | TMM_R3 | UIMM16 | UIMM32 | UIMM8 | UIMM8_1 | UIMMV | UISA_VMODRM_XMM | UISA_VMODRM_YMM | UISA_VMODRM_ZMM | UISA_VSIB_BASE | UISA_VSIB_INDEX_XMM | UISA_VSIB_INDEX_YMM | UISA_VSIB_INDEX_ZMM | UISA_VSIB_XMM | UISA_VSIB_YMM | UISA_VSIB_ZMM | VGPR32_B | VGPR32_B_32 | VGPR32_B_64 | VGPR32_N | VGPR32_N_32 | VGPR32_N_64 | VGPR32_R | VGPR32_R_32 | VGPR32_R_64 | VGPR64_B | VGPR64_N | VGPR64_R | VGPRY_B | VGPRY_N | VGPRY_R | VMODRM_XMM | VMODRM_YMM | VSIB_BASE | VSIB_INDEX_XMM | VSIB_INDEX_YMM | VSIB_XMM | VSIB_YMM | X87 | XMM_B | XMM_B3 | XMM_B3_32 | XMM_B3_64 | XMM_B_32 | XMM_B_64 | XMM_N | XMM_N3 | XMM_N3_32 | XMM_N3_64 | XMM_N_32 | XMM_N_64 | XMM_R | XMM_R3 | XMM_R3_32 | XMM_R3_64 | XMM_R_32 | XMM_R_64 | XMM_SE | XMM_SE32 | XMM_SE64 | XOP_INSTRUCTIONS | YMM_B | YMM_B3 | YMM_B3_32 | YMM_B3_64 | YMM_B_32 | YMM_B_64 | YMM_N | YMM_N3 | YMM_N3_32 | YMM_N3_64 | YMM_N_32 | YMM_N_64 | YMM_R | YMM_R3 | YMM_R3_32 | YMM_R3_64 | YMM_R_32 | YMM_R_64 | YMM_SE | YMM_SE32 | YMM_SE64 | ZMM_B3 | ZMM_B3_32 | ZMM_B3_64 | ZMM_N3 | ZMM_N3_32 | ZMM_N3_64 | ZMM_R3 | ZMM_R3_32 | ZMM_R3_64 let nonterminal_len = 285 let nonterminal_to_int : nonterminal -> int = Obj.magic let nonterminal_of_int (x : int) : nonterminal = if 0 <= x && x < 285 then Obj.magic x else failwith "nonterminal_of_int: no enum for given int" type operand = | INVALID | ABSBR | AGEN | AMD3DNOW | ASZ | BASE0 | BASE1 | BCAST | BCRC | BRDISP_WIDTH | CET | CHIP | CLDEMOTE | DEFAULT_SEG | DF32 | DF64 | DISP | DISP_WIDTH | DUMMY | EASZ | ELEMENT_SIZE | ENCODER_PREFERRED | ENCODE_FORCE | EOSZ | ERROR | ESRC | EVVSPACE | FIRST_F2F3 | HAS_EGPR | HAS_MODRM | HAS_SIB | HINT | ICLASS | ILD_F2 | ILD_F3 | ILD_SEG | IMM0 | IMM0SIGNED | IMM1 | IMM1_BYTES | IMM_WIDTH | INDEX | LAST_F2F3 | LLRC | LOCK | LZCNT | MAP | MASK | MAX_BYTES | MEM0 | MEM1 | MEM_WIDTH | MOD | MODE | MODEP5 | MODEP55C | MODE_FIRST_PREFIX | MODE_SHORT_UD0 | MODRM_BYTE | MPXMODE | MUST_USE_EVEX | ND | NEEDREX | NEED_MEMDISP | NEED_SIB | NELEM | NF | NOMINAL_OPCODE | NOREX | NOREX2 | NO_APX | NO_EVEX | NO_VEX | NPREFIXES | NREXES | NSEG_PREFIXES | OSZ | OUTREG | OUT_OF_BYTES | P4 | POS_DISP | POS_IMM | POS_IMM1 | POS_MODRM | POS_NOMINAL_OPCODE | POS_SIB | PREFIX66 | PTR | REALMODE | REG | REG0 | REG1 | REG2 | REG3 | REG4 | REG5 | REG6 | REG7 | REG8 | REG9 | RELBR | REP | REX | REX2 | REXB | REXB4 | REXR | REXR4 | REXW | REXX | REXX4 | RM | ROUNDC | SAE | SCALE | SCC | SEG0 | SEG1 | SEG_OVD | SIBBASE | SIBINDEX | SIBSCALE | SKIP_OSZ | SMODE | SRM | TZCNT | UBIT | UIMM0 | UIMM1 | USING_DEFAULT_SEGMENT0 | USING_DEFAULT_SEGMENT1 | VEXDEST210 | VEXDEST3 | VEXDEST4 | VEXVALID | VEX_C4 | VEX_PREFIX | VL | VL_IGN | WBNOINVD | ZEROING let operand_len = 141 let operand_to_int : operand -> int = Obj.magic let operand_of_int (x : int) : operand = if 0 <= x && x < 141 then Obj.magic x else failwith "operand_of_int: no enum for given int" type operand_action = | INVALID | RW | R | W | RCW | CW | CRW | CR let operand_action_len = 8 let operand_action_to_int : operand_action -> int = Obj.magic let operand_action_of_int (x : int) : operand_action = if 0 <= x && x < 8 then Obj.magic x else failwith "operand_action_of_int: no enum for given int" type operand_convert = | INVALID | ZEROSTR | SAESTR | ROUNDC | BCASTSTR | MULTIREG_START | MULTIREG2 | MULTIREG3 | MULTIREG4 | MULTIREG5 | MULTIREG6 | MULTIREG7 | MULTIREG8 | MULTIREG9 | MULTIREG10 | MULTIREG11 | MULTIREG12 | MULTIREG13 | MULTIREG14 | MULTIREG15 | MULTIREG16 let operand_convert_len = 21 let operand_convert_to_int : operand_convert -> int = Obj.magic let operand_convert_of_int (x : int) : operand_convert = if 0 <= x && x < 21 then Obj.magic x else failwith "operand_convert_of_int: no enum for given int" type operand_element_type = | INVALID | UINT | INT | SINGLE | DOUBLE | LONGDOUBLE | LONGBCD | STRUCT | VARIABLE | FLOAT16 | BFLOAT16 | INT8 | UINT8 let operand_element_type_len = 13 let operand_element_type_to_int : operand_element_type -> int = Obj.magic let operand_element_type_of_int (x : int) : operand_element_type = if 0 <= x && x < 13 then Obj.magic x else failwith "operand_element_type_of_int: no enum for given int" type operand_element_xtype = | INVALID | A2BF16 | A2F16 | A2I16 | A2U16 | A4I8 | A4U8 | B80 | BF16 | F16 | F32 | F64 | F80 | I1 | I128 | I16 | I32 | I64 | I8 | INT | STRUCT | U128 | U16 | U256 | U32 | U64 | U8 | UINT | VAR let operand_element_xtype_len = 29 let operand_element_xtype_to_int : operand_element_xtype -> int = Obj.magic let operand_element_xtype_of_int (x : int) : operand_element_xtype = if 0 <= x && x < 29 then Obj.magic x else failwith "operand_element_xtype_of_int: no enum for given int" type operand_type = | INVALID | ERROR | IMM | IMM_CONST | NT_LOOKUP_FN | NT_LOOKUP_FN2 | NT_LOOKUP_FN4 | REG let operand_type_len = 8 let operand_type_to_int : operand_type -> int = Obj.magic let operand_type_of_int (x : int) : operand_type = if 0 <= x && x < 8 then Obj.magic x else failwith "operand_type_of_int: no enum for given int" type operand_visibility = | INVALID | EXPLICIT | IMPLICIT | SUPPRESSED let operand_visibility_len = 4 let operand_visibility_to_int : operand_visibility -> int = Obj.magic let operand_visibility_of_int (x : int) : operand_visibility = if 0 <= x && x < 4 then Obj.magic x else failwith "operand_visibility_of_int: no enum for given int" type operand_width = | INVALID | ASZ | SSZ | PSEUDO | PSEUDOX87 | A16 | A32 | B | D | I8 | U8 | I16 | U16 | I32 | U32 | I64 | U64 | F16 | F32 | F64 | DQ | XUB | XUW | XUD | XUQ | X128 | XB | XW | XD | XQ | ZB | ZW | ZD | ZQ | MB | MW | MD | MQ | M64INT | M64REAL | MEM108 | MEM14 | MEM16 | MEM16INT | MEM28 | MEM32INT | MEM32REAL | MEM80DEC | MEM80REAL | F80 | MEM94 | MFPXENV | MXSAVE | MPREFETCH | P | P2 | PD | PS | PI | Q | S | S64 | SD | SI | SS | V | Y | W | Z | SPW8 | SPW | SPW5 | SPW3 | SPW2 | I1 | I2 | I3 | I4 | I5 | I6 | I7 | VAR | BND32 | BND64 | PMMSZ16 | PMMSZ32 | QQ | YUB | YUW | YUD | YUQ | Y128 | YB | YW | YD | YQ | YPS | YPD | ZBF16 | VV | ZV | WRD | MSKW | ZMSKW | ZF32 | ZF64 | ZUB | ZUW | ZUD | ZUQ | ZI8 | ZI16 | ZI32 | ZI64 | ZU8 | ZU16 | ZU32 | ZU64 | ZU128 | M384 | PTR | TMEMROW | TMEMCOL | M512 | TV | ZF16 | Z2F16 | YU | ZD0 let operand_width_len = 129 let operand_width_to_int : operand_width -> int = Obj.magic let operand_width_of_int (x : int) : operand_width = if 0 <= x && x < 129 then Obj.magic x else failwith "operand_width_of_int: no enum for given int" type reg = | INVALID | BNDCFGU | BNDSTATUS | BND0 | BND1 | BND2 | BND3 | CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 | CR13 | CR14 | CR15 | DR0 | DR1 | DR2 | DR3 | DR4 | DR5 | DR6 | DR7 | FLAGS | EFLAGS | RFLAGS | AX | CX | DX | BX | SP | BP | SI | DI | R8W | R9W | R10W | R11W | R12W | R13W | R14W | R15W | R16W | R17W | R18W | R19W | R20W | R21W | R22W | R23W | R24W | R25W | R26W | R27W | R28W | R29W | R30W | R31W | EAX | ECX | EDX | EBX | ESP | EBP | ESI | EDI | R8D | R9D | R10D | R11D | R12D | R13D | R14D | R15D | R16D | R17D | R18D | R19D | R20D | R21D | R22D | R23D | R24D | R25D | R26D | R27D | R28D | R29D | R30D | R31D | RAX | RCX | RDX | RBX | RSP | RBP | RSI | RDI | R8 | R9 | R10 | R11 | R12 | R13 | R14 | R15 | R16 | R17 | R18 | R19 | R20 | R21 | R22 | R23 | R24 | R25 | R26 | R27 | R28 | R29 | R30 | R31 | AL | CL | DL | BL | SPL | BPL | SIL | DIL | R8B | R9B | R10B | R11B | R12B | R13B | R14B | R15B | R16B | R17B | R18B | R19B | R20B | R21B | R22B | R23B | R24B | R25B | R26B | R27B | R28B | R29B | R30B | R31B | AH | CH | DH | BH | ERROR | RIP | EIP | IP | K0 | K1 | K2 | K3 | K4 | K5 | K6 | K7 | MMX0 | MMX1 | MMX2 | MMX3 | MMX4 | MMX5 | MMX6 | MMX7 | SSP | IA32_U_CET | MXCSR | STACKPUSH | STACKPOP | GDTR | LDTR | IDTR | TR | TSC | TSCAUX | MSRS | FSBASE | GSBASE | TILECONFIG | IA32_KERNEL_GS_BASE | DFV0 | DFV1 | DFV2 | DFV3 | DFV4 | DFV5 | DFV6 | DFV7 | DFV8 | DFV9 | DFV10 | DFV11 | DFV12 | DFV13 | DFV14 | DFV15 | X87CONTROL | X87STATUS | X87TAG | X87PUSH | X87POP | X87POP2 | X87OPCODE | X87LASTCS | X87LASTIP | X87LASTDS | X87LASTDP | ES | CS | SS | DS | FS | GS | TMP0 | TMP1 | TMP2 | TMP3 | TMP4 | TMP5 | TMP6 | TMP7 | TMP8 | TMP9 | TMP10 | TMP11 | TMP12 | TMP13 | TMP14 | TMP15 | TMM0 | TMM1 | TMM2 | TMM3 | TMM4 | TMM5 | TMM6 | TMM7 | UIF | ST0 | ST1 | ST2 | ST3 | ST4 | ST5 | ST6 | ST7 | XCR0 | XMM0 | XMM1 | XMM2 | XMM3 | XMM4 | XMM5 | XMM6 | XMM7 | XMM8 | XMM9 | XMM10 | XMM11 | XMM12 | XMM13 | XMM14 | XMM15 | XMM16 | XMM17 | XMM18 | XMM19 | XMM20 | XMM21 | XMM22 | XMM23 | XMM24 | XMM25 | XMM26 | XMM27 | XMM28 | XMM29 | XMM30 | XMM31 | YMM0 | YMM1 | YMM2 | YMM3 | YMM4 | YMM5 | YMM6 | YMM7 | YMM8 | YMM9 | YMM10 | YMM11 | YMM12 | YMM13 | YMM14 | YMM15 | YMM16 | YMM17 | YMM18 | YMM19 | YMM20 | YMM21 | YMM22 | YMM23 | YMM24 | YMM25 | YMM26 | YMM27 | YMM28 | YMM29 | YMM30 | YMM31 | ZMM0 | ZMM1 | ZMM2 | ZMM3 | ZMM4 | ZMM5 | ZMM6 | ZMM7 | ZMM8 | ZMM9 | ZMM10 | ZMM11 | ZMM12 | ZMM13 | ZMM14 | ZMM15 | ZMM16 | ZMM17 | ZMM18 | ZMM19 | ZMM20 | ZMM21 | ZMM22 | ZMM23 | ZMM24 | ZMM25 | ZMM26 | ZMM27 | ZMM28 | ZMM29 | ZMM30 | ZMM31 let reg_len = 365 let reg_invalid_first = INVALID let reg_bndcfg_first = BNDCFGU let reg_bndcfg_last = BNDCFGU let reg_bndstat_first = BNDSTATUS let reg_bndstat_last = BNDSTATUS let reg_bound_first = BND0 let reg_bound_last = BND3 let reg_cr_first = CR0 let reg_cr_last = CR15 let reg_dr_first = DR0 let reg_dr_last = DR7 let reg_flags_first = FLAGS let reg_flags_last = RFLAGS let reg_gpr16_first = AX let reg_gpr16_last = R31W let reg_gpr32_first = EAX let reg_gpr32_last = R31D let reg_gpr64_first = RAX let reg_gpr64_last = R31 let reg_gpr8_first = AL let reg_gpr8_last = R31B let reg_GPR8h_FIRST = AH let reg_GPR8h_LAST = BH let reg_invalid_last = ERROR let reg_ip_first = RIP let reg_ip_last = IP let reg_mask_first = K0 let reg_mask_last = K7 let reg_mmx_first = MMX0 let reg_mmx_last = MMX7 let reg_msr_first = SSP let reg_msr_last = IA32_U_CET let reg_mxcsr_first = MXCSR let reg_mxcsr_last = MXCSR let reg_pseudo_first = STACKPUSH let reg_pseudo_last = DFV15 let reg_pseudox87_first = X87CONTROL let reg_pseudox87_last = X87LASTDP let reg_sr_first = ES let reg_sr_last = GS let reg_tmp_first = TMP0 let reg_tmp_last = TMP15 let reg_treg_first = TMM0 let reg_treg_last = TMM7 let reg_uif_first = UIF let reg_uif_last = UIF let reg_x87_first = ST0 let reg_x87_last = ST7 let reg_xcr_first = XCR0 let reg_xcr_last = XCR0 let reg_xmm_first = XMM0 let reg_xmm_last = XMM31 let reg_ymm_first = YMM0 let reg_ymm_last = YMM31 let reg_zmm_first = ZMM0 let reg_zmm_last = ZMM31 let reg_to_int : reg -> int = Obj.magic let reg_of_int (x : int) : reg = if 0 <= x && x < 365 then Obj.magic x else failwith "reg_of_int: no enum for given int" type reg_class = | INVALID | BNDCFG | BNDSTAT | BOUND | CR | DR | FLAGS | GPR | GPR16 | GPR32 | GPR64 | GPR8 | IP | MASK | MMX | MSR | MXCSR | PSEUDO | PSEUDOX87 | SR | TMP | TREG | UIF | X87 | XCR | XMM | YMM | ZMM let reg_class_len = 28 let reg_class_to_int : reg_class -> int = Obj.magic let reg_class_of_int (x : int) : reg_class = if 0 <= x && x < 28 then Obj.magic x else failwith "reg_class_of_int: no enum for given int" type syntax = | INVALID | XED | ATT | INTEL let syntax_len = 4 let syntax_to_int : syntax -> int = Obj.magic let syntax_of_int (x : int) : syntax = if 0 <= x && x < 4 then Obj.magic x else failwith "syntax_of_int: no enum for given int"